sminv

SVE Signed Minimum Reduction

SMINV <Vd>, <Pg>, <Zn>.<T>

Finds min signed element in vector.

Details

SVE signed minimum reduction: finds the minimum signed element in vector Zn according to predicate mask Pg, and stores the result as a scalar in Vd. The operation reads all active elements from Zn, compares them as signed integers (element size determined by sz), and reduces to a single scalar value. No NZCV flags are affected by this instruction.

Pseudocode Operation

bits(esize) result = MAX_INT(esize);
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    if element < result (signed) then result = element;
Vd[0 +: esize] ← result;

Example

SMINV v0.4s, p0/m, z1.s.T

Encoding

Binary Layout
00000100
size
0010
1
0
001
Pg
Zn
Vd
 
Format SVE Reduction
Opcode 0x040A2000
Extension SVE

Operands

  • Vd
    Dest Scalar
  • Pg
    Mask
  • Zn
    Vector

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E31A800 SMINV <V><d>, <Vn>.<T> A64 0 | Q | 0 | 01110 | size | 11000 | 1 | 101010 | Rn | Rd
0x040A2000 SMINV <V><d>, <Pg>, <Zn>.<T> A64 00000100 | size | 0010 | 1 | 0 | 001 | Pg | Zn | Vd

Description

Signed minimum horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as the maximum signed integer for the element size.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
integer minimum = if unsigned then (2^esize - 1) else (2^(esize-1) - 1);

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer element = Int(Elem[operand, e, esize], unsigned);
        minimum = Min(minimum, element);

V[d, esize] = minimum<esize-1:0>;