vabs

Vector Absolute Value

VABS<c>.<dt> <Qd>, <Qm>

Calculates absolute value of integer/float elements.

Details

NEON Vector Absolute Value: computes the absolute value of each element in Qm and stores the result in Qd. Supports integer (8, 16, 32 bits) and floating-point (32 bits) data types as specified by sz. NEON flags are not modified; no general condition flags are affected.

Pseudocode Operation

for i = 0 to num_elements(Qd, dt) - 1
  Qd[i] ← abs(Qm[i])

Example

VABS.dt q0, q2

Encoding

Binary Layout
111100111
D
11
size
01
Vd
0
F
110
0
M
0
Vm
 
Format NEON 2-Reg
Opcode 0xF3B10300
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B10300 VABS{<c>}{<q>}.<dt> <Dd>, <Dm> A32 111100111 | D | 11 | size | 01 | Vd | 0 | F | 110 | 0 | M | 0 | Vm
0xF3B10340 VABS{<c>}{<q>}.<dt> <Qd>, <Qm> A32 111100111 | D | 11 | size | 01 | Vd | 0 | F | 110 | 1 | M | 0 | Vm
0x0EB009C0 VABS{<c>}{<q>}.F16 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm
0x0EB00AC0 VABS{<c>}{<q>}.F32 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm
0x0EB00BC0 VABS{<c>}{<q>}.F64 <Dd>, <Dm> A32 cond | 11101 | D | 11 | 0 | 000 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm
0xFFB10300 VABS{<c>}{<q>}.<dt> <Dd>, <Dm> T32 111111111 | D | 11 | size | 01 | Vd | 0 | F | 110 | 0 | M | 0 | Vm
0xFFB10340 VABS{<c>}{<q>}.<dt> <Qd>, <Qm> T32 111111111 | D | 11 | size | 01 | Vd | 0 | F | 110 | 1 | M | 0 | Vm
0xEEB009C0 VABS{<c>}{<q>}.F16 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 000 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm
0xEEB00AC0 VABS{<c>}{<q>}.F32 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 000 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm
0xEEB00BC0 VABS{<c>}{<q>}.F64 <Dd>, <Dm> T32 111011101 | D | 11 | 0 | 000 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm

Description

Vector Absolute takes the absolute value of each element in a vector, and places the results in a second vector. The floating-point version only clears the sign bit. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
    if advsimd then  // Advanced SIMD instruction
        for r = 0 to regs-1
            for e = 0 to elements-1
                if floating_point then
                    Elem[D[d+r],e,esize] = FPAbs(Elem[D[m+r],e,esize]);
                else
                    result = Abs(SInt(Elem[D[m+r],e,esize]));
                    Elem[D[d+r],e,esize] = result<esize-1:0>;
    else             // VFP instruction
        case esize of
            when 16 S[d] = Zeros(16) : FPAbs(S[m]<15:0>);
            when 32 S[d] = FPAbs(S[m]);
            when 64 D[d] = FPAbs(D[m]);