uaddv

SVE Unsigned Integer Add Reduction

UADDV <Vd>, <Pg>, <Zn>.<T>

Sums all active unsigned elements into a scalar result.

Details

SVE unsigned integer addition reduction that sums all active elements in the source vector under predicate control and writes the scalar result to the destination. The destination is a general-purpose scalar register sized according to the element type. Elements where the predicate is false are excluded from the sum. NZCV flags are not affected by this reduction.

Pseudocode Operation

result ← 0
for i = 0 to VL/element_size-1:
  if Pg[i] then
    result ← result + Zn[i]
Vd ← result

Example

UADDV v0.4s, p0/m, z1.s.T

Encoding

Binary Layout
00000100
size
0000
0
1
001
Pg
Zn
Vd
 
Format SVE Reduction
Opcode 0x04012000
Extension SVE

Operands

  • Vd
    Dest Scalar
  • Pg
    Mask
  • Zn
    Vector

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x04012000 UADDV <Dd>, <Pg>, <Zn>.<T> A64 00000100 | size | 0000 | 0 | 1 | 001 | Pg | Zn | Vd

Description

Unsigned add horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Narrow elements are first zero-extended to 64 bits. Inactive elements in the source vector are treated as zero.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
integer sum = 0;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer element = UInt(Elem[operand, e, esize]);
        sum = sum + element;

V[d, 64] = sum<63:0>;