bfc

Bit Field Clear

BFC<c> <Rd>, #<lsb>, #<width>

Clears a bitfield in a register.

Details

Clears a contiguous bitfield in a 32-bit register, setting bits from lsb to (lsb+width-1) to zero while preserving all other bits. No condition flags are affected. This is an A32 instruction where the condition code (cond) field determines execution; width is computed as (msb−lsb+1).

Pseudocode Operation

width ← msb - lsb + 1
mask ← ((1 << width) - 1) << lsb
Rd ← Rd AND NOT(mask)

Example

BFC r0, #0, #width

Encoding

Binary Layout
cond
0111110
msb
Rd
lsb
001
1111
 
Format Data Proc
Opcode 0x07C0001F
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • lsb
    Start Bit
  • width
    Width

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x07C0001F BFC{<c>}{<q>} <Rd>, #<lsb>, #<width> A32 cond | 0111110 | msb | Rd | lsb | 001 | 1111
0xF36F0000 BFC{<c>}{<q>} <Rd>, #<lsb>, #<width> T32 11110 | 0 | 11 | 01 | 1 | 0 | 1111 | 0 | imm3 | Rd | imm2 | 0 | msb

Description

Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    R[d]<msbit:lsbit> = Replicate('0', (msbit-lsbit)+1);
    // Other bits of R[d] are unchanged