aesmc

AES Mix Columns (A32)

AESMC.8 <Qd>, <Qm>

AES Mix Columns transformation.

Pseudocode Operation

Qd ← AESMixColumns(Qm)

Example

AESMC.8 q0, q2

Encoding

Binary Layout

11110011

31:24

1

23

D

22

11

21:20

00

19:18

10

17:16

Vd

15:12

00110

11:7

Q

6

M

5

0

4

Vm

3:0

 

Format Crypto 2-Reg

Opcode 0xF3B00380

Extension Crypto

Operands

• Qd
  Destination 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register

Related

Other forms of aesmc

• aesmc AES Mix Columns

More in Crypto

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x4E286800	AESMC <Vd>.16B, <Vn>.16B		A64		01001110 | 00 | 101000011 | 0 | 10 | Rn | Rd
0x4520E000	AESMC <Zdn>.B, <Zdn>.B		A64		01000101 | 0 | 0 | 10000011100 | 0 | 00000 | Zdn

Description

AES mix columns.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) operand = V[n, 128];
bits(128) result;
result = AESMixColumns(operand);
V[d, 128] = result;