tsb

Trace Synchronization Barrier

TSB CSYNC

Ensures trace generation is complete.

Details

Trace Synchronization Barrier with CSYNC variant. Ensures that all trace generation for instructions prior to this barrier is complete before resuming. Provides a synchronization point for trace capture mechanisms. Does not affect condition flags. AArch64-only; requires trace generation support.

Pseudocode Operation

TraceSynchronizationBarrier()

Example

TSB CSYNC

Encoding

Binary Layout

11010101000000110010

0010

010

11111

Format System Hint

Opcode 0xD503225F

Extension Trace

Operands

Reference (Arm A64 ISA)

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xD503225F	TSB CSYNC		A64		11010101000000110010 \| 0010 \| 010 \| 11111

Description

Trace Synchronization Barrier. This instruction is a barrier that synchronizes the trace operations of instructions, see Trace Synchronization Barrier (TSB). If FEAT_TRF is not implemented, this instruction executes as a NOP.

Operation

TraceSynchronizationBarrier();