esb

Error Synchronization Barrier (A32)

ESB

Synchronizes system errors (v8.2).

Pseudocode Operation

// Synchronize error handling
ErrorSynchronizationBarrier()
// All pending error detection and processing operations complete

Encoding

Binary Layout

cond

31:28

00110

27:23

21:20

0000

19:16

000000010000

11:0

Format System Hint

Opcode 0x0320F010

Extension A32 (RAS)

Operands

Other forms of esb

esb Error Synchronization Barrier

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0320F010	ESB{<c>}{<q>}		A32		cond \| 00110 \| 0 \| 10 \| 0000 \| 1 \| 1 \| 1 \| 1 \| 000000010000
0xF3AF8010	ESB{<c>}{<q>}		T32		111100111010 \| 1 \| 1 \| 1 \| 1 \| 10 \| 0 \| 0 \| 0 \| 000 \| 0001 \| 0000

Description

Error Synchronization Barrier is an error synchronization event that might also update DISR and VDISR. This instruction can be used at all Exception levels and in Debug state. In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels. See Error Synchronization Barrier in the ARM(R) Reliability, Availability, and Serviceability (RAS) Specification, Armv8, for Armv8-A architecture profile. If the RAS Extension is not implemented, this instruction executes as a NOP.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();

    SynchronizeErrors();
    AArch32.ESBOperation();
    if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then AArch32.vESBOperation();
    TakeUnmaskedSErrorInterrupts();

esb