fcsel

Floating-Point Conditional Select (Scalar)

FCSEL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <cond>

Selects one of two floats based on condition flags.

Pseudocode Operation

if ConditionHolds(cond) then
  Vd ← Vn
else
  Vd ← Vm

Example

FCSEL Dd, Dn, Dm, cond

Encoding

Binary Layout
0
31
0
30
0
29
11110
28:24
00
23:22
1
21
Rm
20:16
cond
15:12
11
11:10
Rn
9:5
Rd
4:0
 
Format FP Data Processing
Opcode 0x1E200C00
Extension Floating Point

Operands

  • Hd|Sd|Dd
    Destination SIMD&FP register (half, single or double-precision)
  • Hn|Sn|Dn
    First source SIMD&FP register (half, single or double-precision)
  • Hm|Sm|Dm
    Second source SIMD&FP register (half, single or double-precision)
  • cond
    Condition

Related

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1EE00C00 FCSEL <Hd>, <Hn>, <Hm>, <cond> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | cond | 11 | Rn | Rd
0x1E200C00 FCSEL <Sd>, <Sn>, <Sm>, <cond> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | cond | 11 | Rn | Rd
0x1E600C00 FCSEL <Dd>, <Dn>, <Dm>, <cond> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | cond | 11 | Rn | Rd

Description

Floating-point Conditional Select (scalar). This instruction allows the SIMD&FP destination register to take the value from either one or the other of two SIMD&FP source registers. If the condition passes, the first SIMD&FP source register value is taken, otherwise the second SIMD&FP source register value is taken. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(datasize) result;

boolean condition_holds = ConditionHolds(cond);
result = if condition_holds then V[n, datasize] else V[m, datasize];


V[d, datasize] = result;