fcsel

Floating-Point Conditional Select (Scalar)

FCSEL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <cond>

Selects one of two floats based on condition flags.

Details

Selects between two floating-point scalar values based on the current condition flags, writing the selected value to the destination register. If the condition is true, Vn is selected; otherwise, Vm is selected. This is an AArch64-only instruction that does not modify condition flags or any register other than the destination.

Pseudocode Operation

if ConditionHolds(cond) then
  Vd ← Vn
else
  Vd ← Vm

Example

FCSEL Dd, Dn, Dm, cond

Encoding

Binary Layout
0
0
0
11110
00
1
Rm
cond
11
Rn
Rd
 
Format FP Data Processing
Opcode 0x1E200C00
Extension Floating Point

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    Src True
  • Vm
    Src False
  • cond
    Condition

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1EE00C00 FCSEL <Hd>, <Hn>, <Hm>, <cond> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | cond | 11 | Rn | Rd
0x1E200C00 FCSEL <Sd>, <Sn>, <Sm>, <cond> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | cond | 11 | Rn | Rd
0x1E600C00 FCSEL <Dd>, <Dn>, <Dm>, <cond> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | cond | 11 | Rn | Rd

Description

Floating-point Conditional Select (scalar). This instruction allows the SIMD&FP destination register to take the value from either one or the other of two SIMD&FP source registers. If the condition passes, the first SIMD&FP source register value is taken, otherwise the second SIMD&FP source register value is taken. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(datasize) result;

boolean condition_holds = ConditionHolds(cond);
result = if condition_holds then V[n, datasize] else V[m, datasize];


V[d, datasize] = result;