strh.w

Store Register Halfword (Wide)

STRH.W <Rt>, [<Rn>, #<imm>]

Thumb-2 32-bit Store Halfword.

Details

Store the lowest 16 bits of Rt to memory at address [Rn + imm12]. The immediate offset is unsigned and ranges from 0 to 4095 bytes; the halfword must be 2-byte aligned. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

Pseudocode Operation

address ← Rn + ZeroExtend(imm12, 32);
[address]<15:0> ← Rt<15:0>;

Example

STRH.W r3, [r1, #16]

Encoding

Binary Layout
111110001
01
0
Rn
Rt
imm12
 
Format Thumb Store
Opcode 0xF8A00000
Extension T32 (Thumb2)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x014000B0 STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}] A32 cond | 000 | 1 | U | 1 | 0 | 0 | Rn | Rt | imm4H | 1 | 01 | 1 | imm4L
0x004000B0 STRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> A32 cond | 000 | 0 | U | 1 | 0 | 0 | Rn | Rt | imm4H | 1 | 01 | 1 | imm4L
0x016000B0 STRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! A32 cond | 000 | 1 | U | 1 | 1 | 0 | Rn | Rt | imm4H | 1 | 01 | 1 | imm4L
0x8000 STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] T32 1000 | 0 | imm5 | Rn | Rt
0xF8A00000 STRH{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}] T32 111110001 | 01 | 0 | Rn | Rt | imm12
0xF8200C00 STRH{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}] T32 111110000 | 01 | 0 | Rn | Rt | 1 | 1 | 0 | 0 | imm8
0xF8200900 STRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> T32 111110000 | 01 | 0 | Rn | Rt | 1 | 0 | U | 1 | imm8
0xF8200D00 STRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! T32 111110000 | 01 | 0 | Rn | Rt | 1 | 1 | U | 1 | imm8
0x010000B0 STRH{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>] A32 cond | 000 | 1 | U | 0 | 0 | 0 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 01 | 1 | Rm
0x000000B0 STRH{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm> A32 cond | 000 | 0 | U | 0 | 0 | 0 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 01 | 1 | Rm
0x012000B0 STRH{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>]! A32 cond | 000 | 1 | U | 0 | 1 | 0 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 01 | 1 | Rm
0x5200 STRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] T32 0101 | 0 | 0 | 1 | Rm | Rn | Rt
0xF8200000 STRH{<c>}.W <Rt>, [<Rn>, {+}<Rm>] T32 111110000 | 01 | 0 | Rn | Rt | 000000 | imm2 | Rm

Description

Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

Operation

if CurrentInstrSet() == InstrSet_A32 then
    if ConditionPassed() then
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        MemU[address,2] = R[t]<15:0>;
        if wback then R[n] = offset_addr;
else
    if ConditionPassed() then
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        MemU[address,2] = R[t]<15:0>;
        if wback then R[n] = offset_addr;