eor

SVE Bitwise Exclusive OR (Predicated)

EOR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Bitwise XOR of two vectors under predicate.

Details

Performs element-wise bitwise exclusive OR (XOR) between two SVE vector registers under predicate control. Only elements where the corresponding predicate bit is 1 are updated; others are left unchanged. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

Pseudocode Operation

for i = 0 to VL/esize-1 do
  if Pg[i] then
    Zdn[i*esize +: esize] ← Zdn[i*esize +: esize] EOR Zm[i*esize +: esize]
  else
    // element unchanged
endfor

Example

EOR z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout
00000100
size
011
00
1
000
Pg
Zm
Zdn
 
Format SVE Logic
Opcode 0x04190000
Extension SVE

Operands

  • Zdn
    Combined destination/source scalable vector register (SVE)
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E201C00 EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 00 | 1 | Rm | 00011 | 1 | Rn | Rd
0x52000000 EOR <Wd|WSP>, <Wn>, #<imm> A64 0 | 10 | 100100 | 0 | immr | imms | Rn | Rd
0xD2000000 EOR <Xd|SP>, <Xn>, #<imm> A64 1 | 10 | 100100 | N | immr | imms | Rn | Rd
0x4A000000 EOR <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 10 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0xCA000000 EOR <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 10 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x25004200 EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 0 | 0 | 00 | Pm | 01 | Pg | 1 | Pn | 0 | Pd
0x04190000 EOR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 011 | 00 | 1 | 000 | Pg | Zm | Zdn
0x05400000 EOR <Zdn>.<T>, <Zdn>.<T>, #<const> A64 00000101 | 0 | 1 | 0000 | imm13 | Zdn
0x04A03000 EOR <Zd>.D, <Zn>.D, <Zm>.D A64 00000100 | 1 | 0 | 1 | Zm | 001100 | Zn | Zd

Description

Bitwise exclusive OR active elements of the second source vector with corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    bits(esize) element1 = Elem[operand1, e, esize];
    bits(esize) element2 = Elem[operand2, e, esize];
    if ActivePredicateElement(mask, e, esize) then
        Elem[result, e, esize] = element1 EOR element2;
    else
        Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn, VL] = result;