strt

Store Register Unprivileged

STRT<c> <Rt>, [<Rn>, #+/-<imm>]

Stores a word using User Mode permissions.

Details

Stores a 32-bit word to memory using User Mode access permissions, regardless of current privilege level. The T suffix indicates unprivileged (User mode) access is enforced. No condition flags are affected. This is an A32 instruction.

Pseudocode Operation

address ← Rn + (if U then imm12 else -imm12); Mem[address, 4] ← Rt[31:0];

Example

STRT r3, [r1, #+/-#16]

Encoding

Binary Layout
cond
010
0
U
0
1
0
Rn
Rt
imm12
 
Format Load/Store
Opcode 0x04200000
Extension A32 (Base)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x04200000 STRT{<c>}{<q>} <Rt>, [<Rn>] {, #{+/-}<imm>} A32 cond | 010 | 0 | U | 0 | 1 | 0 | Rn | Rt | imm12
0x06200000 STRT{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} A32 cond | 011 | 0 | U | 0 | 1 | 0 | Rn | Rt | imm5 | stype | 0 | Rm
0xF8400E00 STRT{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] T32 111110000 | 10 | 0 | Rn | Rt | 1110 | imm8

Description

Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see Memory accesses. The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode. STRT is unpredictable in Hyp mode. The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    if PSTATE.EL == EL2 then UNPREDICTABLE;               // Hyp mode
    offset = if register_form then Shift(R[m], shift_t, shift_n, PSTATE.C) else imm32;
    offset_addr = if add then (R[n] + offset) else (R[n] - offset);
    address = if postindex then R[n] else offset_addr;
    bits(32) data;
    if t == 15 then  // Only possible for encodings A1 and A2
        data = PCStoreValue();
    else
        data = R[t];
    MemU_unpriv[address,4] = data;
    if postindex then R[n] = offset_addr;