vmov

Vector Move (Core <-> VFP)

VMOV<c> <Sn>, <Rt>

Moves data between Core registers (R) and VFP registers (S).

Details

Moves a 32-bit value between a core integer register (Rt) and a VFP single-precision register (Sn). The instruction transfers the bit pattern without interpretation; a floating-point value moved to a core register is treated as raw bits. Condition flags are not affected. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.

Pseudocode Operation

Sn ← Rt (bit-exact transfer)

Example

VMOV s1, r3

Encoding

Binary Layout
cond
1110000
0
Vn
Rt
1010
N
0
0
1
0
0
0
0
 
Format VFP Transfer
Opcode 0x0E000A10
Extension VFP (Float)

Operands

  • Sn
    VFP Reg
  • Rt
    Core Reg

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0C400B10 VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2> A32 cond | 11000 | 1 | 0 | 0 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0x0C500B10 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm> A32 cond | 11000 | 1 | 0 | 1 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0xEC400B10 VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2> T32 111011000 | 1 | 0 | 0 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0xEC500B10 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm> T32 111011000 | 1 | 0 | 1 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0x0E000910 VMOV{<c>}{<q>}.F16 <Sn>, <Rt> A32 cond | 1110000 | 0 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0x0E100910 VMOV{<c>}{<q>}.F16 <Rt>, <Sn> A32 cond | 1110000 | 1 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xEE000910 VMOV{<c>}{<q>}.F16 <Sn>, <Rt> T32 11101110000 | 0 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xEE100910 VMOV{<c>}{<q>}.F16 <Rt>, <Sn> T32 11101110000 | 1 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xF2800010 VMOV{<c>}{<q>}.I32 <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4
0xF2800050 VMOV{<c>}{<q>}.I32 <Qd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 0 | 1 | imm4
0x0EB00900 VMOV{<c>}{<q>}.F16 <Sd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 01 | 0 | 0 | 0 | 0 | imm4L
0x0EB00A00 VMOV{<c>}{<q>}.F32 <Sd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 10 | 0 | 0 | 0 | 0 | imm4L
0x0EB00B00 VMOV{<c>}{<q>}.F64 <Dd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 11 | 0 | 0 | 0 | 0 | imm4L
0xF2800810 VMOV{<c>}{<q>}.I16 <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4

Description

Copy a general-purpose register to or from a 32-bit SIMD&FP register. This instruction transfers the value held in a 32-bit SIMD&FP register to a general-purpose register, or the value held in a general-purpose register to a 32-bit SIMD&FP register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    if to_arm_register then
        R[t] = S[n];
    else
        S[n] = R[t];