strexd

Store Register Exclusive Double (A32)

STREXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>]

Stores a doubleword if address is still exclusive.

Pseudocode Operation

address ← Rn; if ExclusiveMonitorsCheckExclusive(address, ProcessorID(), 8) then MemU[address, 8] ← Rt || Rt2; Rd ← 0; ExclusiveMonitorsClearExclusive(ProcessorID()); else Rd ← 1;

Example

STREXD r0, r3, r4, [r1]

Encoding

Binary Layout

cond

31:28

00011

27:23

01

22:21

0

20

Rn

19:16

Rd

15:12

1

11

1

10

1

9

1

8

1001

7:4

Rt

3:0

 

Format Load/Store Excl

Opcode 0x01A00F90

Extension A32 (Atomic)

Operands

• Rd
  Status
• Rt
  Transfer general-purpose register (load/store)
• Rt2
  Second transfer register (load/store pair)
• Rn
  First source / base general-purpose register

Related

More in A32 (Atomic)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x01A00F90	STREXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>]		A32		cond | 00011 | 01 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt
0xE8C00070	STREXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>]		T32		11101000110 | 0 | Rn | Rt | Rt2 | 01 | 11 | Rd

Description

Store Register Exclusive Doubleword derives an address from a base register value, stores a 64-bit doubleword from two registers to the derived address if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];

    // Create doubleword to store such that R[t] will be stored at address and R[t2] at address+4.
    value = if BigEndian(AccessType_GPR) then R[t]:R[t2] else R[t2]:R[t];

    if AArch32.ExclusiveMonitorsPass(address,8) then
        MemA[address,8] = value;
        R[d] = ZeroExtend('0', 32);
    else
        R[d] = ZeroExtend('1', 32);