stlrh

Store-Release Register Halfword

STLRH <Wt>, [<Xn|SP>]

Stores a halfword with Release semantics.

Details

Stores a halfword from Wt to memory at the address in Xn with Release semantics, ensuring all prior memory operations are observed before the store completes. This is an AArch64-only instruction used for synchronization in multi-threaded code. No condition flags are affected.

Pseudocode Operation

[Xn] ← Wt<15:0>; Release semantics applied

Example

STLRH w3, [x1]

Encoding

Binary Layout
01
0010001
0
0
11111
1
11111
Rn
Rt
 
Format Load/Store
Opcode 0x489FFC00
Extension Base (Atomic)

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x489FFC00 STLRH <Wt>, [<Xn|SP>{, #0}] A64 01 | 0010001 | 0 | 0 | 11111 | 1 | 11111 | Rn | Rt

Description

Store-Release Register Halfword stores a halfword from a 32-bit register to a memory location. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(16) data;

AccessDescriptor accdesc;
accdesc = CreateAccDescAcqRel(MemOp_STORE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, 0, accdesc);
data = X[t, 16];
Mem[address, 2, accdesc] = data;