lsr

Logical Shift Right (A32)

LSR{S}<c> <Rd>, <Rm>, <Rs>

Shifts a register right.

Details

Logical Shift Right shifts the value in Rm right by the number of bits specified in the lower byte of Rs, filling vacated bits with zeros. The C flag is set to the last bit shifted out, and if the S bit is set, the N and Z flags are updated based on the result. This is an A32 instruction available in all privilege levels.

Pseudocode Operation

shift_amount ← Rs[7:0]
if shift_amount == 0 then
  Rd ← Rm
  if S == 1 then C ← C
else if shift_amount < 32 then
  Rd ← Rm >> shift_amount
  if S == 1 then C ← Rm[shift_amount - 1]
else if shift_amount == 32 then
  Rd ← 0
  if S == 1 then C ← Rm[31]
else
  Rd ← 0
  if S == 1 then C ← 0
if S == 1 then
  N ← Rd[31]
  Z ← (Rd == 0)
  V ← V

Example

LSR r0, r2, r6

Encoding

Binary Layout
cond
00011
01
0
0000
Rd
Rs
0
01
1
Rm
 
Format Data Proc
Opcode 0x01A00030
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rm
    Second source / offset general-purpose register
  • Rs
    Shift amount general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01A00020 LSR{<c>}{<q>} {<Rd>,} <Rm>, #<imm> A32 cond | 00011 | 01 | 0 | 0000 | Rd | imm5 | 01 | 0 | Rm
0x0800 LSR<c>{<q>} {<Rd>,} <Rm>, #<imm> T32 000 | 01 | imm5 | Rm | Rd
0xEA4F0010 LSR<c>.W {<Rd>,} <Rm>, #<imm> T32 1110101 | 0010 | 0 | 1111 | 0 | imm3 | Rd | imm2 | 01 | Rm
0x01A00030 LSR{<c>}{<q>} {<Rd>,} <Rm>, <Rs> A32 cond | 00011 | 01 | 0 | 0000 | Rd | Rs | 0 | 01 | 1 | Rm
0x40C0 LSR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> T32 010000 | 0011 | Rs | Rdm
0xFA20F000 LSR<c>.W {<Rd>,} <Rm>, <Rs> T32 111110100 | 01 | 0 | Rm | 1111 | Rd | 0000 | Rs

Description

shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register