ldrsh

Load Register Signed Halfword (A32)

LDRSH<c> <Rt>, [<Rn>, #+/-<imm>]

Loads a halfword and sign-extends it.

Pseudocode Operation

offset ← ZeroExtend(imm4H:imm4L) << 1;
if U == 1 then address ← Rn + offset else address ← Rn - offset;
if P == 1 then address ← address else address ← Rn;
Rt ← SignExtend(MemRead(address, 2));
if W == 1 then Rn ← address;

Example

LDRSH r3, [r1, #+/-#16]

Encoding

Binary Layout

cond

31:28

000

27:25

1

24

U

23

1

22

1

21

1

20

Rn

19:16

Rt

15:12

imm4H

11:8

1

7

11

6:5

1

4

imm4L

3:0

 

Format Load/Store

Opcode 0x017000F0

Extension A32 (Base)

Operands

• Rt
  Transfer general-purpose register (load/store)
• Rn
  First source / base general-purpose register

Related

More in A32 (Base)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x015000F0	LDRSH{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}]		A32		cond | 000 | 1 | U | 1 | 0 | 1 | Rn | Rt | imm4H | 1 | 11 | 1 | imm4L
0x005000F0	LDRSH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>		A32		cond | 000 | 0 | U | 1 | 0 | 1 | Rn | Rt | imm4H | 1 | 11 | 1 | imm4L
0x017000F0	LDRSH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!		A32		cond | 000 | 1 | U | 1 | 1 | 1 | Rn | Rt | imm4H | 1 | 11 | 1 | imm4L
0xF9B00000	LDRSH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]		T32		111110011 | 01 | 1 | Rn | Rt | imm12
0xF9300C00	LDRSH{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}]		T32		111110010 | 01 | 1 | Rn | Rt | 1 | 1 | 0 | 0 | imm8
0xF9300900	LDRSH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>		T32		111110010 | 01 | 1 | Rn | Rt | 1 | 0 | U | 1 | imm8
0xF9300D00	LDRSH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!		T32		111110010 | 01 | 1 | Rn | Rt | 1 | 1 | U | 1 | imm8
0x005F00F0	LDRSH{<c>}{<q>} <Rt>, <label>		A32		cond | 000 | P | U | 1 | W | 1 | 1111 | Rt | imm4H | 1 | 11 | 1 | imm4L
0xF93F0000	LDRSH{<c>}{<q>} <Rt>, <label>		T32		11111001 | U | 01 | 11111 | Rt | imm12
0x011000F0	LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>]		A32		cond | 000 | 1 | U | 0 | 0 | 1 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 11 | 1 | Rm
0x001000F0	LDRSH{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>		A32		cond | 000 | 0 | U | 0 | 0 | 1 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 11 | 1 | Rm
0x013000F0	LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>]!		A32		cond | 000 | 1 | U | 0 | 1 | 1 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 11 | 1 | Rm
0x5E00	LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>]		T32		0101 | 1 | 1 | 1 | Rm | Rn | Rt
0xF9300000	LDRSH{<c>}.W <Rt>, [<Rn>, {+}<Rm>]		T32		111110010 | 01 | 1 | Rn | Rt | 000000 | imm2 | Rm

Description

Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
    address = if index then offset_addr else R[n];
    data = MemU[address,2];
    if wback then R[n] = offset_addr;
    R[t] = SignExtend(data, 32);