umin

Vector Unsigned Minimum

UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Returns smaller unsigned integer per element.

Details

Vector Unsigned Minimum compares corresponding unsigned integer elements in two NEON registers and places the smaller value into the destination register, operating element-wise according to the element type T. This instruction operates on all elements within the vector (128-bit if Q=1, 64-bit if Q=0) and does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

Pseudocode Operation

for i = 0 to elements_in_vector(Q, size) - 1 do
  Vd[i] ← min_unsigned(Vn[i], Vm[i])
end for

Example

UMIN v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
1
01110
size
1
Rm
0110
1
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x2E206C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E206C00 UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | size | 1 | Rm | 0110 | 1 | 1 | Rn | Rd
0x11CC0000 UMIN <Wd>, <Wn>, #<uimm> A64 0 | 0 | 0 | 1000111 | 0011 | imm8 | Rn | Rd
0x91CC0000 UMIN <Xd>, <Xn>, #<uimm> A64 1 | 0 | 0 | 1000111 | 0011 | imm8 | Rn | Rd
0xC120A021 UMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101000 | 0000 | 1 | Zdn | 1
0xC120A821 UMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101010 | 0000 | 1 | Zdn | 0 | 1
0xC120B021 UMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } A64 11000001 | size | 1 | Zm | 0101100 | 000 | 0 | 1 | Zdn | 1
0xC120B821 UMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } A64 11000001 | size | 1 | Zm | 00101110 | 000 | 0 | 1 | Zdn | 0 | 1
0x1AC06C00 UMIN <Wd>, <Wn>, <Wm> A64 0 | 0 | 0 | 11010110 | Rm | 011011 | Rn | Rd
0x9AC06C00 UMIN <Xd>, <Xn>, <Xm> A64 1 | 0 | 0 | 11010110 | Rm | 011011 | Rn | Rd
0x040B0000 UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 001 | 0 | 1 | 1 | 000 | Pg | Zm | Zdn
0x252BC000 UMIN <Zdn>.<T>, <Zdn>.<T>, #<imm> A64 00100101 | size | 101 | 01 | 1 | 11 | 0 | imm8 | Zdn

Description

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
integer element1;
integer element2;
integer maxmin;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
    Elem[result, e, esize] = maxmin<esize-1:0>;

V[d, datasize] = result;