ARM Instructions
1157 instructions — click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| abs | ABS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Integer Unary | SVE | Calculates absolute value of integers. |
| abs | ABS <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Calculates absolute value of integer elements. |
| adc | ADC <Wd>, <Wn>, <Wm> | Data Processing (3-source) | Base | Adds two register values and the Carry flag. |
| adc | ADC <Xd>, <Xn>, <Xm> | Data Processing (3-source) | Base | Adds two 64-bit register values and the Carry flag. |
| adc | ADC{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Adds two 32-bit values and the Carry flag. |
| adc.w | ADC.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit add with carry (Access high registers/large constants). |
| adcs | ADCS <Wd>, <Wn>, <Wm> | Data Processing (3-source) | Base | Adds two register values and Carry, updating NZCV flags. |
| adcs | ADCS <Xd>, <Xn>, <Xm> | Data Processing (3-source) | Base | Adds two 64-bit register values and Carry, updating NZCV flags. |
| add | ADD <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing (Register) | Base | Adds a register value and a sign/zero-extended register value. |
| add | ADD <Xd|SP>, <Xn|SP>, <R><m> {, <extend> {#<amount>}} | Data Processing (Register) | Base | Adds a 64-bit register and an extended register value. |
| add | ADD <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Base | Adds a register value and an immediate value. |
| add | ADD <Xd|SP>, <Xn|SP>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Base | Adds a 64-bit register value and an immediate value. |
| add | ADD <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing (Register) | Base | Adds a register value and a shifted register value. |
| add | ADD <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Data Processing (Register) | Base | Adds a 64-bit register value and a shifted register value. |
| add | ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds corresponding elements in two vectors. |
| add | ADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Adds two vectors under predicate control. |
| add | ADD{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Adds two 32-bit values. |
| add.w | ADD.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit add. |
| addg | ADDG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> | Data Processing | MTE (Memory Tagging) | Adds an immediate to an address, modifying the Allocation Tag (MTE). |
| addp | ADDP <Dd>, <Vn>.<T> | NEON Scalar | NEON (Scalar) | Adds two 64-bit values to a 64-bit result (Scalar NEON). |
| addp | ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds adjacent pairs of elements. |
| adds | ADDS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing (Register) | Base | Adds and updates flags (Extended Register). |
| adds | ADDS <Xd>, <Xn|SP>, <R><m> {, <extend> {#<amount>}} | Data Processing (Register) | Base | Adds and updates flags (Extended Register 64-bit). |
| adds | ADDS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Base | Adds immediate and updates flags. |
| adds | ADDS <Xd>, <Xn|SP>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Base | Adds immediate and updates flags (64-bit). |
| adds | ADDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing (Register) | Base | Adds shifted register and updates flags. |
| adds | ADDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Data Processing (Register) | Base | Adds shifted register and updates flags (64-bit). |
| addv | ADDV <V><d>, <Vn>.<T> | SIMD Across Lane | NEON (SIMD) | Adds all elements of the vector into a scalar result. |
| adr | ADR <Xd>, <label> | PC-rel | Base | Calculates the address of a label (PC +/- 1MB range). |
| adr | ADR <Rd>, <label> | Thumb Data Proc | T32 (Thumb) | Adds an immediate value to the PC (Thumb). |
| adr | ADR<c> <Rd>, <label> | Data Proc | A32 (Base) | Adds an immediate value to the PC register. |
| adr.w | ADR.W <Rd>, <label> | Thumb Data Proc | T32 (Thumb2) | Thumb-2 32-bit ADR. |
| adrp | ADRP <Xd>, <label> | PC-rel | Base | Calculates page address of a label (PC +/- 4GB range). |
| aesd | AESD.8 <Qd>, <Qm> | Crypto 2-Reg | Crypto | Performs one round of AES decryption (AArch32). |
| aesd | AESD <Vd>.16B, <Vm>.16B | Crypto | Crypto | AES single round decryption (AArch64 NEON). |
| aesd | AESD <Vd>.<T>, <Vn>.<T> | Crypto | Crypto | Performs one round of AES decryption. |
| aese | AESE.8 <Qd>, <Qm> | Crypto 2-Reg | Crypto | Performs one round of AES encryption (AArch32). |
| aese | AESE <Vd>.16B, <Vm>.16B | Crypto | Crypto | AES single round encryption (AArch64 NEON). |
| aese | AESE <Vd>.<T>, <Vn>.<T> | Crypto | Crypto | Performs one round of AES encryption. |
| aesimc | AESIMC.8 <Qd>, <Qm> | Crypto 2-Reg | Crypto | AES Inverse Mix Columns transformation. |
| aesimc | AESIMC <Vd>.<T>, <Vn>.<T> | Crypto | Crypto | Performs AES Inverse Mix Columns transformation. |
| aesmc | AESMC.8 <Qd>, <Qm> | Crypto 2-Reg | Crypto | AES Mix Columns transformation. |
| aesmc | AESMC <Vd>.<T>, <Vn>.<T> | Crypto | Crypto | Performs AES Mix Columns transformation. |
| and | AND <Wd|Wsp>, <Wn>, #<imm> | Logical (Immediate) | Base | Bitwise AND with logical immediate. |
| and | AND <Xd|SP>, <Xn>, #<imm> | Logical (Immediate) | Base | Bitwise AND with logical immediate (64-bit). |
| and | AND <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | Bitwise AND with shifted register. |
| and | AND <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Base | Bitwise AND with shifted register (64-bit). |
| and | AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Bitwise AND of two vectors. |
| and | AND <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE | Bitwise AND of two vectors under predicate. |
| and | AND{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Performs a bitwise AND on two 32-bit values. |
| and.w | AND.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit AND. |
| ands | ANDS <Wd>, <Wn>, #<imm> | Logical (Immediate) | Base | Bitwise AND immediate, updates flags. |
| ands | ANDS <Xd>, <Xn>, #<imm> | Logical (Immediate) | Base | Bitwise AND immediate, updates flags (64-bit). |
| ands | ANDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | Bitwise AND shifted register, updates flags. |
| ands | ANDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Base | Bitwise AND shifted register, updates flags (64-bit). |
| andv | ANDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | ANDs all active elements into a scalar. |
| asr | ASR <Wd>, <Wn>, #<shift> | Data Processing (Immediate) | Base | Arithmetic shift right by immediate. |
| asr | ASR <Xd>, <Xn>, #<shift> | Data Processing (Immediate) | Base | Arithmetic shift right by immediate (64-bit). |
| asr | ASR <Wd>, <Wn>, <Wm> | Data Processing (Register) | Base | Arithmetic shift right by register value. |
| asr | ASR <Xd>, <Xn>, <Xm> | Data Processing (Register) | Base | Arithmetic shift right by register value (64-bit). |
| asr | ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Shift | SVE | Shifts elements right arithmetically under predicate. |
| asr | ASR{S}<c> <Rd>, <Rm>, <Rs> | Data Proc | A32 (Base) | Arithmetic right shift (sign-extending). |
| at | AT S1E1R, <Xt> | System | Base (System) | Performs stage 1 address translation for current EL. |
| at | AT S1E1W, <Xt> | System | Base (System) | Performs stage 1 address translation for write permission. |
| at | AT <op>, <Xt> | System Alias | System | Translates a virtual address to a physical address (for debug/software). |
| autda | AUTDA <Xd>, <Xn> | Data Processing | PAC (Security) | Authenticates a data address signed with Key A. |
| autdb | AUTDB <Xd>, <Xn> | Data Processing | PAC (Security) | Authenticates a data address signed with Key B. |
| autia | AUTIA <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Authenticates a pointer signed with Key A. Corrupts pointer if failed. |
| autia | AUTIA <Xd>, <Xn> | Data Processing | PAC (Security) | Authenticates an instruction address signed with Key A. |
| autib | AUTIB <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Authenticates a pointer signed with Key B. |
| autib | AUTIB <Xd>, <Xn> | Data Processing | PAC (Security) | Authenticates an instruction address signed with Key B. |
| b | B <label> | Branch | Base | Unconditional branch to label. |
| b | B<c> <label> | Branch | A32 (Base) | Branch relative (PC +/- 32MB). |
| b.cond | B.cond <label> | Branch | Base | Branch if condition is met (e.g., B.EQ, B.NE). |
| b.w | B.W <label> | Thumb Branch | T32 (Thumb2) | Thumb-2 32-bit Unconditional Branch (large range). |
| bc.cond | BC.cond <label> | Branch | Base (v8.8) | Branch if condition is met, with stronger ordering guarantees. |
| bfadd | BFADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | FEAT_SVE_B16B16 | Adds BFloat16 elements. |
| bfc | BFC <Rd>, #<lsb>, #<width> | Thumb Bitfield | A32 (Base) | Clears a bitfield in a register. |
| bfc | BFC<c> <Rd>, #<lsb>, #<width> | Data Proc | A32 (Base) | Clears a bitfield in a register. |
| bfcvtn | BFCVTN <Vd>.<Tb>, <Vn>.<Ta> | NEON 2-Reg | FEAT_BF16 (AI) | Converts Float32 to BFloat16 (Lower Half). |
| bfcvtn2 | BFCVTN2 <Vd>.<Tb>, <Vn>.<Ta> | NEON 2-Reg | FEAT_BF16 (AI) | Converts Float32 to BFloat16 (Upper Half). |
| bfdot | BFDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_BF16 (AI) | Computes dot product of BFloat16 elements, accumulating to Float32 (NEON). |
| bfi | BFI <Rd>, <Rn>, #<lsb>, #<width> | Thumb Bitfield | A32 (Base) | Inserts a bitfield into a register. |
| bfi | BFI<c> <Rd>, <Rn>, #<lsb>, #<width> | Data Proc | A32 (Base) | Copies a bitfield into a register. |
| bfm | BFM <Wd>, <Wn>, #<immr>, #<imms> | Bitfield | Base | Moves a bitfield from source to destination. |
| bfm | BFM <Xd>, <Xn>, #<immr>, #<imms> | Bitfield | Base | Moves a bitfield from source to destination (64-bit). |
| bfmax | BFMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | FEAT_SVE_B16B16 | Calculates maximum of BFloat16 elements. |
| bfmin | BFMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | FEAT_SVE_B16B16 | Calculates minimum of BFloat16 elements. |
| bfmmla | BFMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_BF16 (AI) | Performs 2x2 matrix multiplication on BFloat16 tiles (NEON). |
| bfmul | BFMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | FEAT_SVE_B16B16 | Multiplies BFloat16 elements. |
| bfsub | BFSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | FEAT_SVE_B16B16 | Subtracts BFloat16 elements. |
| bic | BIC <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | ANDs register with NOT of shifted register (AND NOT). |
| bic | BIC <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Base | ANDs register with NOT of shifted register (64-bit). |
| bic | BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | ANDs Vd with NOT of Vm. |
| bic | BIC <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE | Bitwise AND NOT of two vectors under predicate. |
| bic | BIC{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Performs AND NOT (Rd = Rn & ~Rm). |
| bic.w | BIC.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit AND NOT. |
| bics | BICS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | Performs BIC and updates flags. |
| bics | BICS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Base | Performs BIC and updates flags (64-bit). |
| bif | BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Inserts bits from Vn into Vd where Vm (mask) is 0. |
| bit | BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Inserts bits from Vn into Vd where Vm (mask) is 1. |
| bkpt | BKPT #<imm> | Thumb System | T32 (Thumb) | Software Breakpoint (Thumb encoding). |
| bkpt | BKPT #<imm> | System | A32 (Base) | Causes a software breakpoint. |
| bl | BL <label> | Branch | Base | Function call. Branches to label and stores return address in LR (X30). |
| bl | BL<c> <label> | Branch | A32 (Base) | Calls a subroutine, storing return address in LR (R14). |
| bl.w | BL.W <label> | Thumb Branch | T32 (Thumb2) | Thumb-2 32-bit Branch with Link. |
| blr | BLR <Xn> | Branch (Reg) | Base | Indirect function call. Branches to address in Xn and stores return in LR. |
| blx | BLX<c> <Rm> | Branch | A32 (Base) | Calls subroutine and optionally switches to Thumb state. |
| br | BR <Xn> | Branch (Reg) | Base | Indirect branch to address in Xn. |
| brb | BRB <op> | System | FEAT_BRBE (Debug) | Injects an entry into the Branch Record Buffer (Debug). |
| brbtsy | BRBTSY | System | FEAT_BRBE (Debug) | Synchronizes the BRBE timestamp. |
| brk | BRK #<imm> | Exception | Base | Generates a Breakpoint instruction exception. |
| brka | BRKA <Pd>.B, <Pg>/Z, <Pn>.B | SVE Predicate | SVE | Sets predicates up to and including the first active element. |
| brkb | BRKB <Pd>.B, <Pg>/Z, <Pn>.B | SVE Predicate | SVE | Sets predicates up to (but excluding) the first active element. |
| bsl | BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Selects bits from Vn or Vm based on Vd (mask). (Vd = (Vd & Vn) | (~Vd & Vm)). |
| bti | BTI <target> | System Hint | BTI (Security) | Marks a valid target for indirect branches (Guard against JOP/ROP). |
| bti | BTI {<target>} | System | BTI (Security) | Mark a valid target for an indirect branch (Control Flow Integrity). |
| bx | BX<c> <Rm> | Branch | A32 (Base) | Branches to address in register, optionally switching ISA. |
| bxj | BXJ<c> <Rm> | Branch | A32 (Legacy) | Legacy instruction to enter Jazelle state (Now behaves like BX). |
| cas | CAS <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic Compare and Swap (32-bit). |
| cas | CAS <Xs>, <Xt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic Compare and Swap (64-bit). |
| casa | CASA <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic CAS with Acquire semantics. |
| casal | CASAL <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic CAS with Acquire and Release semantics. |
| casl | CASL <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic CAS with Release semantics. |
| casp | CASP <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic CAS of a pair of registers (128-bit or 64-bit pair). |
| cbnz | CBNZ <Wt>, <label> | Branch | Base | Branches if register is not zero. |
| cbnz | CBNZ <Xt>, <label> | Branch | Base | Branches if 64-bit register is not zero. |
| cbnz | CBNZ <Rn>, <label> | Thumb Branch | T32 (Thumb) | Branches to label if register is not zero (Thumb-only). |
| cbz | CBZ <Wt>, <label> | Branch | Base | Branches if register is zero. |
| cbz | CBZ <Xt>, <label> | Branch | Base | Branches if 64-bit register is zero. |
| cbz | CBZ <Rn>, <label> | Thumb Branch | T32 (Thumb) | Branches to label if register is zero (Thumb-only, does not affect flags). |
| ccmn | CCMN <Wn>, #<imm>, #<nzcv>, <cond> | Cond Comp | Base | Compares register with negative immediate if condition is true. |
| ccmn | CCMN <Xn>, #<imm>, #<nzcv>, <cond> | Cond Comp | Base | Compares 64-bit register with negative immediate if condition is true. |
| ccmn | CCMN <Wn>, <Wm>, #<nzcv>, <cond> | Cond Comp | Base | Compares two registers (negated) if condition is true. |
| ccmp | CCMP <Wn>, #<imm>, #<nzcv>, <cond> | Cond Comp | Base | Compares register with immediate if condition is true. |
| ccmp | CCMP <Wn>, <Wm>, #<nzcv>, <cond> | Cond Comp | Base | Compares two registers if condition is true. |
| cdp | CDP<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2> | Coprocessor | A32 (System) | Initiates a coprocessor data processing operation. |
| cdp2 | CDP2<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2> | Coprocessor | A32 (System) | Initiates a coprocessor operation (Extension encoding). |
| cfinv | CFINV | System | FEAT_FlagM | Inverts the C (Carry) flag. |
| chk | CHK <#imm> | System | FEAT_CHK | Check feature status (FEAT_CHK). |
| cinc | CINC <Wd>, <Wn>, <cond> | Cond Select | Base | Increment register if condition is true, else copy. (Alias for CSINC) |
| cinv | CINV <Wd>, <Wn>, <cond> | Cond Select | Base | Invert register bits if condition is true, else copy. (Alias for CSINV) |
| clasta | CLASTA <Rdn>, <Pg>, <Rdn>, <Zm>.<T> | SVE Extract | SVE | Extracts element after the last active element. |
| clastb | CLASTB <Rdn>, <Pg>, <Rdn>, <Zm>.<T> | SVE Extract | SVE | Extracts the last active element. |
| clrex | CLREX | Thumb System | A32 (Atomic) | Clears exclusive monitor (Thumb). |
| clrex | CLREX {#<imm>} | System | Base (Atomic) | Clears the local monitor state (AArch64 variant). |
| clrex | CLREX<c> | System | A32 (Base) | Clears the local exclusive access monitor. |
| cls | CLS <Wd>, <Wn> | Data Processing | Base | Counts number of consecutive sign bits. |
| clz | CLZ <Wd>, <Wn> | Data Processing | Base | Counts number of consecutive zeros. |
| clz | CLZ <Rd>, <Rm> | Thumb Misc | A32 (Base) | Counts consecutive zeros. |
| clz | CLZ<c> <Rd>, <Rm> | Data Proc | A32 (Base) | Counts the number of consecutive zeros from MSB. |
| clz | CLZ <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Counts leading zeros for each element. |
| cmeq | CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Compares elements (Vn == Vm) and sets bits to all 1s or 0s. |
| cmge | CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Compares elements (Vn >= Vm). |
| cmgt | CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Compares elements (Vn > Vm) and sets bits to all 1s or 0s. |
| cmn | CMN <Wn>, #<imm> | Data Processing | Base | Adds register and immediate, updates flags (discard result). (Alias for ADDS) |
| cmn | CMN<c> <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Adds two values and updates flags (discarding result). Same as ADDS with no destination. |
| cmn.w | CMN.W <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Compare Negative (Add and update flags). |
| cmp | CMP <Wn>, #<imm> | Data Processing | Base | Subtracts immediate from register, updates flags (discard result). (Alias for SUBS) |
| cmp | CMP<c> <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Subtracts two values and updates flags (discarding result). |
| cmp.w | CMP.W <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Compare (Subtract and update flags). |
| cmpeq | CMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | SVE Compare | SVE | Sets predicate bits where elements are equal. |
| cmpgt | CMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | SVE Compare | SVE | Sets predicate bits where Zn > Zm. |
| cmtst | CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Tests if any bits match ((Vn & Vm) != 0). |
| cneg | CNEG <Wd>, <Wn>, <cond> | Cond Select | Base | Negate register if condition is true, else copy. (Alias for CSNEG) |
| cnt | CNT <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Counts set bits (population count) per byte. |
| cntp | CNTP <Xn>, <Pg>, <Pn>.<T> | SVE Count | SVE | Counts the number of true elements in a predicate. |
| compact | COMPACT <Zd>.<T>, <Pg>, <Zn>.<T> | SVE Permute | SVE | Packs active elements to the bottom of the vector. |
| cosp | COSP <Xt> | System | FEAT_CSV3 | Prevents speculation from reordering beyond this point. |
| cosp | COSP <Xt> | System | FEAT_CSV3 (Speculation) | Prevents speculation from determining that the instruction is executed. |
| cppp | CPPP <Xt> | System | FEAT_CPP | Prevents cache prefetch prediction past this instruction. |
| cps | CPS<effect> <iflags> {, #<mode>} | System | A32 (System) | Changes the processor mode or interrupt masks. |
| cps | CPS<effect> <iflags> {, #<mode>} | Thumb System | A32 (System) | Change mode/state (Thumb). |
| cpy | CPY <Zd>.<T>, <Pg>/M, <R><n> | SVE Move | SVE | Copies scalar value to active vector elements (Alias for DUP predicated). |
| cpy | CPY <Zd>.<T>, <Pg>/M, <Zn>.<T> | SVE2 Move | SVE2 | Copies data from source to destination using SVE vector length. |
| crc32b | CRC32B<c> <Rd>, <Rn>, <Rm> | Data Proc | CRC | CRC32 checksum update (Byte). |
| crc32b | CRC32B <Wd>, <Wn>, <Wm> | Data Processing | CRC | Updates CRC32 checksum with a byte. |
| crc32cb | CRC32CB <Wd>, <Wn>, <Wm> | Data Processing | CRC | Updates CRC32C (Castagnoli) checksum with a byte. |
| crc32w | CRC32W<c> <Rd>, <Rn>, <Rm> | Data Proc | CRC | CRC32 checksum update (Word). |
| crc32w | CRC32W <Wd>, <Wn>, <Wm> | Data Processing | CRC | Updates CRC32 checksum with a word. |
| crc32x | CRC32X <Wd>, <Wn>, <Xm> | Data Processing | CRC | Updates CRC32 checksum with a doubleword (64-bit). |
| csdb | CSDB | System Hint | A32 (System) | Prevents speculative data consumption. |
| csdb | CSDB | System Hint | A32 (v8.0) | Prevents speculative data consumption (v8.0). |
| csdb | CSDB | System Hint | Base | Prevents speculative data consumption. |
| csel | CSEL <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Base | Selects between two registers based on condition. |
| cset | CSET <Wd>, <cond> | Cond Select | Base | Sets register to 1 if condition true, else 0. (Alias for CSINC) |
| csinc | CSINC <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Base | Selects Wn if cond true, else (Wm + 1). |
| csinv | CSINV <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Base | Selects Wn if cond true, else NOT Wm. |
| csneg | CSNEG <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Base | Selects Wn if cond true, else -Wm. |
| dbg | DBG #<option> | System Hint | A32 (Base) | Provides a hint to the debug system. |
| dbg | DBG #<option> | Thumb System | A32 (Base) | Debug hint (Thumb). |
| dc | DC <op>, <Xt> | System Alias | System | Performs data cache maintenance (Clean, Invalidate, Flush). |
| dcps1 | DCPS1 | System | A32 (System) | Switches execution to EL1 (Debug). |
| dcps1 | DCPS1 {#<imm>} | Exception | System | Switch to Exception Level 1 (Debug). |
| dcps2 | DCPS2 | System | A32 (System) | Switches execution to EL2 (Debug). |
| dcps2 | DCPS2 {#<imm>} | Exception | System | Switch to Exception Level 2 (Debug). |
| dcps3 | DCPS3 | System | A32 (System) | Switches execution to EL3 (Debug). |
| dcps3 | DCPS3 {#<imm>} | Exception | System | Switch to Exception Level 3 (Debug). |
| decb | DECB <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Decrements a register by the number of active bytes. |
| decd | DECD <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Decrements a register by the number of active doublewords. |
| decw | DECW <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Decrements a register by the number of active words. |
| dfb | DFB | System Hint | A32 (Legacy) | Deprecated alias for DSB. |
| dgh | DGH | System Hint | Base | Hints that multiple memory accesses should be merged. |
| dmb | DMB <option> | System | Base | Ensures memory access ordering. |
| dmb | DMB <option> | Thumb System | A32 (Base) | Memory barrier (Thumb). |
| dmb | DMB <option> | System | A32 (Base) | Ensures memory access ordering. |
| drps | DRPS | System | System | Restores state from SPSR_ELx and DLR_EL0. |
| dsb | DSB <option> | System | Base | Ensures completion of memory accesses. |
| dsb | DSB <option> | Thumb System | A32 (Base) | Sync barrier (Thumb). |
| dsb | DSB <option> | System | A32 (Base) | Ensures completion of memory accesses. |
| dup | DUP <Vd>.<T>, <R><n> | SIMD Copy | NEON (SIMD) | Duplicates a general-purpose register to all vector elements. |
| dup | DUP <Vd>.<T>, <Vn>.<Ts>[<index>] | SIMD Copy | NEON (SIMD) | Duplicates a vector element to all elements in destination. |
| dup | DUP <Zd>.<T>, <R><n|m> | SVE Move | SVE | Broadcasts a scalar register or immediate to all active vector elements. |
| eon | EON <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | XORs register with NOT of shifted register (XNOR). |
| eon | EON <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Base | XORs 64-bit register with NOT of shifted register. |
| eor | EOR <Wd|Wsp>, <Wn>, #<imm> | Logical (Immediate) | Base | XORs register with immediate. |
| eor | EOR <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | XORs two registers. |
| eor | EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Bitwise XOR of two vectors. |
| eor | EOR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE | Bitwise XOR of two vectors under predicate. |
| eor | EOR{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Performs bitwise XOR. |
| eor.w | EOR.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit XOR. |
| eorv | EORV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | XORs all active elements into a scalar. |
| eret | ERET | System | Base | Returns from an exception. |
| eret | ERET | System | A32 (System) | Returns from an exception (A32). |
| eret | ERET | Thumb System | A32 (System) | Returns from an exception (Thumb state). |
| esb | ESB | System Hint | A32 (System) | Synchronizes errors. |
| esb | ESB | System Alias | RAS (Reliability) | Synchronizes unrecoverable system errors. |
| esb | ESB | System Hint | A32 (RAS) | Synchronizes system errors (v8.2). |
| ext | EXT <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<imm> | SVE Permute | SVE | Extracts a vector from a pair (sliding window) using immediate byte index. |
| ext | EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index> | SIMD Extract | NEON (SIMD) | Extracts a vector from a pair of vectors (Sliding window). |
| extr | EXTR <Wd>, <Wn>, <Wm>, #<lsb> | Data Processing | Base | Extracts a register from a pair of registers. |
| extr | EXTR <Xd>, <Xn>, <Xm>, #<lsb> | Data Processing | Base | Extracts a 64-bit register from a pair. |
| fabs | FABS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE FP Unary | SVE | Calculates absolute value of floats. |
| fabs | FABS <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Calculates the absolute value of a float. |
| fabs | FABS <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Calculates absolute value for each element. |
| fabs | FABS <Vd>.8H, <Vn>.8H | NEON FP16 | FEAT_FP16 (NEON) | Absolute value of half-precision vector. |
| fadd | FADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Adds two floating-point values. |
| fadd | FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds elements of two floating-point vectors. |
| fadd | FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Adds floating-point elements under predicate. |
| fadd | FADD <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Adds two half-precision floating-point vectors. |
| fadd | FADD <Sd>, <Sn>, <Sm> | Float Data Proc | F.P. | Adds two single-precision floating-point registers. |
| fadd | FADD <Dd>, <Dn>, <Dm> | Float Data Proc | F.P. | Adds two double-precision floating-point registers. |
| faddp | FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds adjacent pairs of float elements. |
| faddv | FADDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Sums all active floating-point elements into a scalar result. |
| fcadd | FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, #<rot> | SVE FP Complex | SVE | Performs complex addition with rotation. |
| fcadd | FCADD <Vd>.4S, <Vn>.4S, <Vm>.4S, #<rot> | NEON Complex | FEAT_FCMA | Complex addition with rotation (NEON). |
| fccmp | FCCMP <Hn|Sn|Dn>, <Hm|Sm|Dm>, #<nzcv>, <cond> | FP Compare | Floating Point | Compares floats only if condition is met, else sets flags to immediate. |
| fcmla | FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, #<rot> | SVE FP Complex | SVE | Performs complex multiply-accumulate. |
| fcmla | FCMLA <Vd>.4S, <Vn>.4S, <Vm>.4S, #<rot> | NEON Complex | FEAT_FCMA | Complex multiply-accumulate with rotation (NEON). |
| fcmp | FCMP <Hn|Sn|Dn>, <Hm|Sm|Dm|#0.0> | FP Compare | Floating Point | Compares two floating-point values and updates process flags (NZCV). |
| fcmp | FCMP <Sn>, <Sm> | Float Compare | F.P. | Compares two single-precision registers and updates NZCV flags. |
| fcmp | FCMP <Dn>, <Dm> | Float Compare | F.P. | Compares two double-precision registers and updates NZCV flags. |
| fcmpeq | FCMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | SVE FP Compare | SVE | Sets predicate bits where float elements are equal. |
| fcmpgt | FCMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | SVE FP Compare | SVE | Sets predicate bits where float Zn > Zm. |
| fcsel | FCSEL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <cond> | FP Data Processing | Floating Point | Selects one of two floats based on condition flags. |
| fcvt | FCVT <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts between float precisions (e.g., Half <-> Single <-> Double). |
| fcvtas | FCVTAS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to signed integer, rounding to nearest. |
| fcvtau | FCVTAU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to unsigned integer, rounding to nearest. |
| fcvtl | FCVTL <Vd>.4S, <Vn>.4H | NEON FP16 | FEAT_FP16 (NEON) | Converts Half-precision (Bottom) to Single-precision. |
| fcvtl | FCVTL <Vd>.<Td>, <Vn>.<Ts> | SIMD Two Register | NEON (SIMD) | Converts narrow floats to wide floats (e.g., Half -> Single). |
| fcvtl2 | FCVTL2 <Vd>.4S, <Vn>.8H | NEON FP16 | FEAT_FP16 (NEON) | Converts Half-precision (Top) to Single-precision. |
| fcvtms | FCVTMS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to signed integer, rounding towards minus infinity (Floor). |
| fcvtmu | FCVTMU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to unsigned integer, rounding towards minus infinity. |
| fcvtn | FCVTN <Vd>.4H, <Vn>.4S | NEON FP16 | FEAT_FP16 (NEON) | Converts Single-precision to Half-precision (Bottom). |
| fcvtn | FCVTN <Vd>.<Td>, <Vn>.<Ts> | SIMD Two Register | NEON (SIMD) | Converts wide floats to narrow floats (e.g., Single -> Half). |
| fcvtn2 | FCVTN2 <Vd>.8H, <Vn>.4S | NEON FP16 | FEAT_FP16 (NEON) | Converts Single-precision to Half-precision (Top). |
| fcvtns | FCVTNS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to signed integer, rounding to nearest (bankers' round). |
| fcvtnu | FCVTNU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to unsigned integer, rounding to nearest (bankers' round). |
| fcvtps | FCVTPS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to signed integer, rounding towards plus infinity (Ceil). |
| fcvtpu | FCVTPU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to unsigned integer, rounding towards plus infinity. |
| fcvtzs | FCVTZS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE | Converts floats to signed integers (Truncate). |
| fcvtzs | FCVTZS <Wd|Xd>, <Hn|Sn|Dn> {, #<fbits>} | FP Conversion | Floating Point | Converts float to signed integer, rounding towards zero (Truncate). |
| fcvtzs | FCVTZS <Xd>, <Dn> | Float Conversion | F.P. | Converts floating-point to signed integer. |
| fcvtzs | FCVTZS <Vd>.<T>, <Vn>.<T> {, #<fbits>} | SIMD Two Register | NEON (SIMD) | Converts floats to signed integers (Truncate). |
| fcvtzu | FCVTZU <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE | Converts floats to unsigned integers (Truncate). |
| fcvtzu | FCVTZU <Wd|Xd>, <Hn|Sn|Dn> {, #<fbits>} | FP Conversion | Floating Point | Converts float to unsigned integer, rounding towards zero (Truncate). |
| fcvtzu | FCVTZU <Vd>.<T>, <Vn>.<T> {, #<fbits>} | SIMD Two Register | NEON (SIMD) | Converts floats to unsigned integers (Truncate). |
| fdiv | FDIV <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Divides two floating-point values. |
| fdiv | FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Divides elements of floating-point vectors. |
| fdiv | FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Divides floating-point elements under predicate. |
| fdiv | FDIV <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Divides two half-precision floating-point vectors. |
| fdiv | FDIV <Sd>, <Sn>, <Sm> | Float Data Proc | F.P. | Divides two single-precision floating-point registers. |
| fdiv | FDIV <Dd>, <Dn>, <Dm> | Float Data Proc | F.P. | Divides two double-precision floating-point registers. |
| fjcvtzs | FJCVTZS <Wd>, <Dn> | Float Convert | FEAT_JSCVT | Converts double to signed 32-bit integer with JS rounding semantics. |
| fmadd | FMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating Point | Calculates (Vn * Vm) + Va without intermediate rounding. |
| fmax | FMAX <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Returns the larger of two values. |
| fmax | FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Compares and returns the larger value per element. |
| fmax | FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Determines maximum value of active float elements. |
| fmax | FMAX <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Finds max of half-precision vectors. |
| fmaxnm | FMAXNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Returns larger value, handling NaNs according to IEEE 754-2008 'maxNum'. |
| fmaxp | FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Max of adjacent float elements. |
| fmaxv | FMAXV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds max float in vector. |
| fmaxv | FMAXV <Sd>, <Vn>.<T> | NEON Reduction | NEON (v8.0) | Finds max float in a vector. |
| fmin | FMIN <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Returns the smaller of two values. |
| fmin | FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Compares and returns the smaller value per element. |
| fmin | FMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Determines minimum value of active float elements. |
| fmin | FMIN <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Finds min of half-precision vectors. |
| fminnm | FMINNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Returns smaller value, handling NaNs according to IEEE 754-2008 'minNum'. |
| fminp | FMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Min of adjacent float elements. |
| fminv | FMINV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds min float in vector. |
| fminv | FMINV <Sd>, <Vn>.<T> | NEON Reduction | NEON (v8.0) | Finds min float in a vector. |
| fmla | FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies and adds to destination (Vd = Vd + Vn * Vm). |
| fmla | FMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> | SVE FP Ternary | SVE | Calculates (Zda + Zn * Zm) under predicate. |
| fmla | FMLA <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Fused multiply-add on half-precision vectors. |
| fmls | FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies and subtracts from destination (Vd = Vd - Vn * Vm). |
| fmls | FMLS <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> | SVE FP Ternary | SVE | Calculates (Zda - Zn * Zm) under predicate. |
| fmls | FMLS <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Fused multiply-subtract on half-precision vectors. |
| fmov | FMOV <Hd|Sd|Dd>, #<fimm> | FP Immediate | Floating Point | Moves a floating-point immediate into a scalar register. |
| fmov | FMOV <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Copies a value from one scalar FP register to another. |
| fmov | FMOV <Wd|Xd>, <Sn|Dn> | FP Conversion | Floating Point | Copies bits between a General-Purpose Register (W/X) and FP Register (S/D). |
| fmov | FMOV <Sd|Dd>, <Wn|Xn> | FP Conversion | Floating Point | Copies bits from a General-Purpose Register (W/X) to FP Register (S/D). |
| fmov | FMOV <Dd>, <Dn> | Float Data Proc | F.P. | Copies value between floating-point registers. |
| fmov | FMOV <Dd>, #<imm> | Float Imm | F.P. | Moves immediate value into floating-point register. |
| fmsub | FMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating Point | Calculates (Vn * Vm) - Va. |
| fmul | FMUL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Multiplies two floating-point values. |
| fmul | FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies elements of floating-point vectors. |
| fmul | FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Multiplies floating-point elements under predicate. |
| fmul | FMUL <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Multiplies two half-precision floating-point vectors. |
| fmul | FMUL <Sd>, <Sn>, <Sm> | Float Data Proc | F.P. | Multiplies two single-precision floating-point registers. |
| fmul | FMUL <Dd>, <Dn>, <Dm> | Float Data Proc | F.P. | Multiplies two double-precision floating-point registers. |
| fneg | FNEG <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE FP Unary | SVE | Negates floats. |
| fneg | FNEG <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Negates the value (flips sign bit). |
| fneg | FNEG <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Negates each element. |
| fneg | FNEG <Vd>.8H, <Vn>.8H | NEON FP16 | FEAT_FP16 (NEON) | Negates half-precision vector. |
| fnmadd | FNMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating Point | Calculates -((Vn * Vm) + Va). |
| fnmsub | FNMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating Point | Calculates -((Vn * Vm) - Va). |
| fnmul | FNMUL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Calculates -(Vn * Vm). |
| frecpe | FRECPE <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Estimates reciprocal (1/x) for floats. |
| frecps | FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Newton-Raphson step for reciprocal refinement. |
| frint32x | FRINT32X <Sd>, <Sn> | Float Conversion | FEAT_FRINTTS | Rounds to 32-bit integer, exact exception. |
| frint32z | FRINT32Z <Sd>, <Sn> | Float Conversion | FEAT_FRINTTS | Rounds to 32-bit integer towards zero. |
| frint64x | FRINT64X <Sd>, <Sn> | Float Conversion | FEAT_FRINTTS | Rounds to 64-bit integer, exact exception. |
| frint64z | FRINT64Z <Sd>, <Sn> | Float Conversion | FEAT_FRINTTS | Rounds to 64-bit integer towards zero. |
| frinta | FRINTA <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to nearest integral value (ties away from zero). |
| frinti | FRINTI <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value using current FPCR rounding mode. |
| frintm | FRINTM <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value towards minus infinity (Floor). |
| frintn | FRINTN <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value nearest, ties to even. |
| frintp | FRINTP <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value towards plus infinity (Ceil). |
| frintx | FRINTX <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value using current mode, raising Inexact exception. |
| frintz | FRINTZ <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Rounds float to integral value towards zero (Truncate). |
| frsqrte | FRSQRTE <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Estimates reciprocal square root (1/sqrt(x)). |
| frsqrts | FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Newton-Raphson step for reciprocal square root refinement. |
| fsqrt | FSQRT <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE FP Unary | SVE | Calculates square root of floats. |
| fsqrt | FSQRT <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Calculates square root. |
| fsqrt | FSQRT <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Calculates square root for each element. |
| fsqrt | FSQRT <Vd>.8H, <Vn>.8H | NEON FP16 | FEAT_FP16 (NEON) | Square root of half-precision vector. |
| fsub | FSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Subtracts two floating-point values. |
| fsub | FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Subtracts elements of floating-point vectors. |
| fsub | FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Subtracts floating-point elements under predicate. |
| fsub | FSUB <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Subtracts two half-precision floating-point vectors. |
| fsub | FSUB <Sd>, <Sn>, <Sm> | Float Data Proc | F.P. | Subtracts two single-precision floating-point registers. |
| fsub | FSUB <Dd>, <Dn>, <Dm> | Float Data Proc | F.P. | Subtracts two double-precision floating-point registers. |
| gcspopm | GCSPOPM | System | FEAT_GCS (Security) | Pops the value from the Guarded Control Stack into LR. |
| gcsss1 | GCSSS1 <Xt> | System | FEAT_GCS (Security) | First step to switch the GCS pointer. |
| gcsss2 | GCSSS2 <Xt> | System | FEAT_GCS (Security) | Second step to switch the GCS pointer. |
| gmi | GMI <Xd>, <Xn|SP>, <Xm> | Data Processing | MTE (Memory Tagging) | Calculates a mask of excluded tags (MTE). |
| hint | HINT #<imm> | System | Base | Provides a hint to the processor (e.g., NOP, YIELD). |
| hlt | HLT #<imm> | Exception | Base | Enters Halting debug mode. |
| hlt | HLT #<imm> | Thumb System | T32 (Thumb) | Enters halting debug state (Thumb encoding). |
| hlt | HLT #<imm> | System | A32 (Base) | Enters halting debug state (A32 encoding). |
| hvc | HVC #<imm> | Exception | System | Generates a Hypervisor Call exception to EL2. |
| hvc | HVC #<imm> | Thumb System | A32 (Virtualization) | Calls the Hypervisor (EL2) from Thumb state. |
| hvc | HVC #<imm> | System | A32 (System) | Calls the Hypervisor (EL2). |
| ic | IC <op> {, <Xt>} | System Alias | System | Performs instruction cache maintenance. |
| incb | INCB <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Increments a general-purpose register by the number of active bytes in the pattern. |
| incd | INCD <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Increments a register by the number of active doublewords. |
| incw | INCW <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Increments a register by the number of active words. |
| index | INDEX <Zd>.<T>, <Start>, <Step> | SVE Index | SVE | Generates a vector of indices: V[i] = Start + i * Step. |
| ins | INS <Vd>.<Ts>[<index>], <Rn> | SIMD Copy | NEON (SIMD) | Moves data from a GPR to a specific vector element. |
| insr | INSR <Zdn>.<T>, <R><m> | SVE Move | SVE | Inserts scalar into bottom of vector, shifting other elements up. |
| irg | IRG <Xd|SP>, <Xn|SP>{, <Xm>} | Data Processing | MTE (Memory Tagging) | Inserts a random Allocation Tag into a pointer (MTE). |
| irg | IRG <Xd|SP>, <Xn|SP> {, <Xm>} | Data Processing | MTE (Memory Tagging) | Inserts a random Tag into a pointer (MTE). |
| isb | ISB {<option>} | System | Base | Flushes the pipeline and prefetches. |
| isb | ISB <option> | Thumb System | A32 (Base) | Instruction barrier (Thumb). |
| isb | ISB <option> | System | A32 (Base) | Flushes the pipeline. |
| it | IT{x{y{z}}} <cond> | Thumb IT | T32 (Thumb) | Makes up to 4 following instructions conditional (Thumb-only). |
| lasta | LASTA <Vd>.<T>, <Pg>, <Zn>.<T> | SVE Extract | SVE | Extracts element after last active (SIMD scalar destination). |
| lastb | LASTB <Vd>.<T>, <Pg>, <Zn>.<T> | SVE Extract | SVE | Extracts last active element (SIMD scalar destination). |
| ld1 | LD1 { <Vt>.<T>, ... }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads one element structure from memory into 1-4 registers. |
| ld1b | LD1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads bytes from memory into a vector under predicate control. |
| ld1d | LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads doublewords from memory into a vector under predicate control. |
| ld1h | LD1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads halfwords from memory into a vector under predicate control. |
| ld1r | LD1R { <Vt>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads one element and replicates it to all lanes of the vector. |
| ld1w | LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads words from memory into a vector under predicate control. |
| ld1w | LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, SXTW #<shift>] | SVE Gather | SVE | Loads words from non-contiguous addresses (Scatter-Gather). |
| ld2 | LD2 { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads two-element structures from memory into two registers (De-interleave). |
| ld2r | LD2R { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads 2 elements and replicates them to all lanes. |
| ld3 | LD3 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads three-element structures (e.g., RGB) into three registers. |
| ld4 | LD4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Loads four-element structures (e.g., RGBA) into four registers. |
| ld64b | LD64B <Xt>, [<Xn|SP>] | Load/Store | LSE (Atomics) | Loads a 64-byte block of data atomically (Accelerator support). |
| lda | LDA<c> <Rt>, [<Rn>] | Load/Store | A32 (Atomic) | Loads a word with Acquire semantics. |
| ldadd | LDADD <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic add to memory, return old value. |
| ldaexb | LDAEXB<c> <Rt>, [<Rn>] | Load Excl | A32 (Atomic) | Loads a byte, acquires semantics, marks exclusive. |
| ldaexd | LDAEXD<c> <Rt>, <Rt2>, [<Rn>] | Load Excl | A32 (Atomic) | Loads a doubleword, acquires semantics, marks exclusive. |
| ldaexh | LDAEXH<c> <Rt>, [<Rn>] | Load Excl | A32 (Atomic) | Loads a halfword, acquires semantics, marks exclusive. |
| ldalex | LDAEX<c> <Rt>, [<Rn>] | Load/Store | A32 (Atomic) | Loads a word with Acquire Exclusive semantics. |
| ldapr | LDAPR <Wt>, [<Xn|SP>] | Load/Store | Base (RCpc) | Loads a word with RCpc Acquire semantics. |
| ldaprb | LDAPRB <Wt>, [<Xn|SP>] | Load/Store | Base (RCpc) | Loads a byte with Release Consistency (process consistent) Acquire semantics. |
| ldaprh | LDAPRH <Wt>, [<Xn|SP>] | Load/Store | Base (RCpc) | Loads a halfword with RCpc Acquire semantics. |
| ldar | LDAR <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Loads a word with Acquire semantics. |
| ldarb | LDARB <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Loads a byte with Acquire semantics. |
| ldarh | LDARH <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Loads a halfword with Acquire semantics. |
| ldaxr | LDAXR <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Loads a word with Acquire Exclusive semantics. |
| ldaxrb | LDAXRB <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Loads a byte with Acquire Exclusive semantics. |
| ldaxrh | LDAXRH <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Loads a halfword with Acquire Exclusive semantics. |
| ldc | LDC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | A32 (System) | Loads memory into a coprocessor. |
| ldc2 | LDC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | A32 (System) | Loads memory into a coprocessor (Extension encoding). |
| ldclr | LDCLR <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic bit clear (AND NOT) to memory. |
| ldeor | LDEOR <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic XOR to memory. |
| ldff1b | LDFF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads bytes speculatively; suppresses faults after the first active element. |
| ldff1d | LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads doublewords speculatively; suppresses faults after the first active element. |
| ldff1h | LDFF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads halfwords speculatively; suppresses faults after the first active element. |
| ldff1w | LDFF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads words speculatively; suppresses faults after the first active element. |
| ldg | LDG <Xt>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Loads the Allocation Tag from memory. |
| ldm | LDM <Rn>!, <registers> | Thumb Load Multiple | A32 (Base) | Load multiple registers (Thumb 16-bit). |
| ldm | LDM<mode><c> <Rn>{!}, <registers> | Load Multiple | A32 (Base) | Loads multiple registers from memory (Stack pop). |
| ldm.w | LDM.W <Rn>{!}, <registers> | Thumb Load Multiple | T32 (Thumb2) | Thumb-2 32-bit Load Multiple. |
| ldnf1b | LDNF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads bytes without faulting; returns 0 if fault occurs. |
| ldnf1d | LDNF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads doublewords without faulting. |
| ldnf1h | LDNF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads halfwords without faulting. |
| ldnf1w | LDNF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] | SVE Load | SVE | Loads words without faulting. |
| ldnp | LDNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Base | Loads two words, hinting non-temporal data (no caching). |
| ldp | LDP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Floating Point | Loads two floating-point/SIMD registers. |
| ldp | LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm> | Load/Store Pair | Base | Loads two words from memory. |
| ldp | LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> | Load/Store Pair | Base | Loads two 64-bit doublewords from memory. |
| ldpsw | LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Base | Loads two words and sign-extends them to 64-bit. |
| ldr | LDR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>] | Load/Store | Floating Point | Loads a floating-point/SIMD register from memory. |
| ldr | LDR <Wt>, [<Xn|SP>, #<pimm>] | Load/Store Imm | Base | Loads a word from memory (Immediate offset). |
| ldr | LDR <Wt>, <label> | Load Literal | Base | Loads a word from a PC-relative address. |
| ldr | LDR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store Reg | Base | Loads a word from memory (Register offset). |
| ldr | LDR<c> <Rt>, <label> | Load Literal | A32 (Base) | Loads a word from a label. |
| ldr | LDR <Rt>, <label> | Thumb Load | T32 (Thumb) | Loads a word from a label (Thumb). |
| ldr | LDR<c> <Rt>, [<Rn>, #+/-<imm>]{!} | Load/Store | A32 (Base) | Loads a word from memory. |
| ldr.w | LDR.W <Rt>, [<Rn>, #<imm>] | Thumb Load | T32 (Thumb2) | Thumb-2 32-bit Load Word. |
| ldraa | LDRAA <Xt>, [<Xn|SP>, #<simm>] | Load/Store | PAC (Security) | Loads a value, authenticating the address with Key A. |
| ldrab | LDRAB <Xt>, [<Xn|SP>, #<simm>] | Load/Store | PAC (Security) | Loads a value, authenticating the address with Key B. |
| ldrb | LDRB <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Loads a byte from memory (zero-extended) using immediate offset. |
| ldrb | LDRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Base | Loads a byte from memory (zero-extended) using register offset. |
| ldrb | LDRB<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a byte from memory (Zero extended). |
| ldrb.w | LDRB.W <Rt>, [<Rn>, #<imm>] | Thumb Load | T32 (Thumb2) | Thumb-2 32-bit Load Byte. |
| ldrbt | LDRBT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a byte using User Mode permissions. |
| ldrd | LDRD <Rt>, <Rt2>, [<Rn>, #+/-<imm>] | Thumb Load | A32 (Base) | Loads two words from memory (Thumb). |
| ldrd | LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads two consecutive words into consecutive registers. |
| ldrex | LDREX <Rt>, [<Rn>] | Thumb Load Excl | A32 (Atomic) | Loads word and sets exclusive monitor (Thumb). |
| ldrex | LDREX<c> <Rt>, [<Rn>] | Load/Store | A32 (Atomic) | Loads a word and marks physical address as exclusive. |
| ldrexb | LDREXB<c> <Rt>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Loads a byte and marks address as exclusive. |
| ldrexb | LDREXB <Rt>, [<Rn>] | Thumb Load Excl | A32 (Atomic) | Loads byte exclusively (Thumb). |
| ldrexd | LDREXD<c> <Rt>, <Rt2>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Loads a doubleword and marks address as exclusive. |
| ldrexh | LDREXH<c> <Rt>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Loads a halfword and marks address as exclusive. |
| ldrexh | LDREXH <Rt>, [<Rn>] | Thumb Load Excl | A32 (Atomic) | Loads halfword exclusively (Thumb). |
| ldrh | LDRH <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Loads a halfword from memory (zero-extended). |
| ldrh | LDRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Base | Loads a halfword from memory (zero-extended) using register offset. |
| ldrh | LDRH<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a halfword (Zero extended). |
| ldrh.w | LDRH.W <Rt>, [<Rn>, #<imm>] | Thumb Load | T32 (Thumb2) | Thumb-2 32-bit Load Halfword. |
| ldrht | LDRHT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a halfword using User Mode permissions. |
| ldrsb | LDRSB <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Loads a byte and sign-extends it to 32-bits. |
| ldrsb | LDRSB <Xt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Loads a byte and sign-extends it to 64-bits. |
| ldrsb | LDRSB<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a byte and sign-extends it. |
| ldrsb.w | LDRSB.W <Rt>, [<Rn>, #<imm>] | Thumb Load | T32 (Thumb2) | Thumb-2 32-bit Load Signed Byte. |
| ldrsbt | LDRSBT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a signed byte using User Mode permissions. |
| ldrsh | LDRSH<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a halfword and sign-extends it. |
| ldrsh.w | LDRSH.W <Rt>, [<Rn>, #<imm>] | Thumb Load | T32 (Thumb2) | Thumb-2 32-bit Load Signed Halfword. |
| ldrsht | LDRSHT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a signed halfword using User Mode permissions. |
| ldrsw | LDRSW <Xt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Loads a word and sign-extends it to 64-bits. |
| ldrsw | LDRSW <Xt>, <label> | Load Literal | Base | Loads a word from PC-relative address and sign-extends to 64-bits. |
| ldrt | LDRT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Loads a word using User Mode permissions (even if Privileged). |
| ldset | LDSET <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic bit set (OR) to memory. |
| ldsmax | LDSMAX <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic signed max to memory. |
| ldsmin | LDSMIN <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic signed min to memory. |
| ldtr | LDTR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Loads a word as if in EL0 (User mode). |
| ldumax | LDUMAX <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic unsigned max to memory. |
| ldumin | LDUMIN <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic unsigned min to memory. |
| ldur | LDUR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Loads a word using an unscaled immediate offset. |
| ldxp | LDXP <Wt1>, <Wt2>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Loads two words as an exclusive operation. |
| ldxr | LDXR <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Loads a word and marks physical address as exclusive access. |
| lsl | LSLV <Wd>, <Wn>, <Wm> | Data Processing | Base | Shifts register left by variable amount. |
| lsl | LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Shift | SVE | Shifts elements left under predicate. |
| lsl | LSL{S}<c> <Rd>, <Rm>, <Rs> | Data Proc | A32 (Base) | Shifts a register left. |
| lsr | LSRV <Wd>, <Wn>, <Wm> | Data Processing | Base | Shifts register right by variable amount. |
| lsr | LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Shift | SVE | Shifts elements right logically under predicate. |
| lsr | LSR{S}<c> <Rd>, <Rm>, <Rs> | Data Proc | A32 (Base) | Shifts a register right. |
| madd | MADD <Wd>, <Wn>, <Wm>, <Wa> | Data Processing | Base | Calculates (Ra + (Rn * Rm)). |
| madd | MADD <Xd>, <Xn>, <Xm>, <Xa> | Data Processing | Base | Calculates (Xa + (Xn * Xm)). |
| mcr | MCR<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | A32 (System) | Writes a general-purpose register to a coprocessor register (e.g., CP15). |
| mcr2 | MCR2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | A32 (System) | Writes a general-purpose register to a coprocessor (Extension encoding). |
| mcrr | MCRR<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | A32 (System) | Writes two general-purpose registers to a coprocessor (64-bit transfer). |
| mcrr2 | MCRR2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | A32 (System) | Writes two registers to a coprocessor (Extension encoding). |
| mia | MIA<c> <Acc>, <Rn>, <Rm> | Coprocessor | A32 (XScale) | Multiplies two 32-bit values and adds to 40-bit internal acc (XScale Legacy). |
| miaph | MIAPH<c> <Acc>, <Rn>, <Rm> | Coprocessor | A32 (XScale) | SIMD multiply of packed halfwords to internal acc (XScale Legacy). |
| mla | MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies elements and adds to destination (Vd = Vd + Vn * Vm). |
| mla | MLA <Rd>, <Rm>, <Ra>, <Rn> | Thumb Mul | A32 (Base) | Rd = Rn + (Rm * Ra). |
| mla | MLA{S}<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (Base) | Calculates Rd = (Rn * Rm) + Ra. |
| mls | MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies elements and subtracts from destination (Vd = Vd - Vn * Vm). |
| mls | MLS <Rd>, <Rm>, <Ra>, <Rn> | Thumb Mul | A32 (Base) | Rd = Rn - (Rm * Ra). |
| mls | MLS<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (Base) | Calculates Rd = Ra - (Rn * Rm). |
| mov | MOV <Vd>.<T>, <Vn>.<T> | SIMD Alias | NEON (SIMD) | Copies a vector register (Alias for ORR Vd, Vn, Vn). |
| mov | MOV <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>] | SIMD Copy | NEON (SIMD) | Moves a vector element to another vector element (Alias for INS). |
| mov | MOV{S}<c> <Rd>, <Operand2> | Data Proc | A32 (Base) | Moves a value into a register. |
| mov.w | MOV.W <Rd>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Move. |
| movi | MOVI <Vd>.<T>, #<imm8> {, lsl #<shift>} | SIMD Modified Imm | NEON (SIMD) | Moves an immediate value into every element of a vector. |
| movk | MOVK <Wd>, #<imm16> {, lsl #<shift>} | Data Processing | Base | Inserts a 16-bit immediate into a register, keeping other bits unchanged. |
| movn | MOVN <Wd>, #<imm16> {, lsl #<shift>} | Data Processing | Base | Moves inverted 16-bit immediate to register. |
| movt | MOVT<c> <Rd>, #<imm16> | Data Proc | A32 (Base) | Writes a 16-bit immediate to the top half of a register. |
| movw | MOVW<c> <Rd>, #<imm16> | Data Proc | A32 (Base) | Writes a 16-bit immediate to the bottom half, zeroing top. |
| movz | MOVZ <Wd>, #<imm16> {, lsl #<shift>} | Data Processing | Base | Moves 16-bit immediate to register, zeroing other bits. |
| mrc | MRC<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | A32 (System) | Reads a coprocessor register into a general-purpose register. |
| mrc2 | MRC2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} | Coprocessor | A32 (System) | Reads a coprocessor register into a general-purpose register (Extension encoding). |
| mrrc | MRRC<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | A32 (System) | Reads a coprocessor register into two general-purpose registers. |
| mrrc2 | MRRC2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> | Coprocessor | A32 (System) | Reads a coprocessor register into two registers (Extension encoding). |
| mrrs | MRRS <Xt>, <Xt+1>, <sysreg> | System | FEAT_SYSREG128 | Reads a 128-bit system register into two general-purpose registers. |
| mrs | MRS <Xt>, <system_reg> | System | System | Moves system register to general-purpose register. |
| mrs | MRS <Rd>, <banked_reg> | System | A32 (System) | Reads a banked register into a general-purpose register. |
| mrs | MRS <Rd>, <spec_reg> | Thumb System | A32 (System) | Read special register (Thumb). |
| mrs | MRS<c> <Rd>, <spec_reg> | System | A32 (System) | Reads CPSR or SPSR. |
| msr | MSR <system_reg>, <Xt> | System | System | Moves general-purpose register to system register. |
| msr | MSR <banked_reg>, <Rn> | System | A32 (System) | Writes to a banked register from a general-purpose register. |
| msr | MSR <spec_reg>, #<imm> | System | A32 (System) | Writes an immediate to a status register (A32). |
| msr | MSR <spec_reg>, #<imm> | Thumb System | T32 (System) | Writes an immediate to a status register (Thumb). |
| msr | MSR <spec_reg>, <Rn> | Thumb System | A32 (System) | Write special register (Thumb). |
| msr | MSR<c> <spec_reg>_<fields>, <Rn> | System | A32 (System) | Writes to CPSR or SPSR. |
| msrr | MSRR <sysreg>, <Xt>, <Xt+1> | System | FEAT_SYSREG128 | Writes two general-purpose registers into a 128-bit system register. |
| msub | MSUB <Wd>, <Wn>, <Wm>, <Wa> | Data Processing | Base | Calculates (Ra - (Rn * Rm)). |
| mul | MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies corresponding elements in two vectors. |
| mul | MUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Multiplies two vectors under predicate. |
| mul | MUL{S}<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (Base) | Multiplies two 32-bit values. |
| mvn | MVN <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Bitwise NOT of a vector. |
| mvn | MVN{S}<c> <Rd>, <Operand2> | Data Proc | A32 (Base) | Moves bitwise inverse of value. |
| mvn.w | MVN.W <Rd>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Move Inverse. |
| mvni | MVNI <Vd>.<T>, #<imm8> {, lsl #<shift>} | SIMD Modified Imm | NEON (SIMD) | Moves the inverse of an immediate value into every element. |
| neg | NEG <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Integer Unary | SVE | Negates integers. |
| neg | NEG <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Negates integer elements. |
| nop | NOP | System Alias | Base | Does nothing. Used for padding or timing. |
| nop | NOP | Thumb System | A32 (Base) | No op (Thumb 16-bit). |
| nop | NOP<c> | System | A32 (Base) | Does nothing. |
| not | NOT <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Integer Unary | SVE | Inverts bits. |
| not | NOT <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Inverts all bits. (Alias for MVN). |
| orn | ORN <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | ORs register with NOT of shifted register. |
| orn | ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | ORs Vd with NOT of Vm. |
| orn.w | ORN.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit OR NOT. |
| orr | ORR <Wd|Wsp>, <Wn>, #<imm> | Logical (Immediate) | Base | ORs register with logical immediate. |
| orr | ORR <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | ORs two registers. |
| orr | ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Bitwise OR of two vectors. |
| orr | ORR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE | Bitwise OR of two vectors under predicate. |
| orr | ORR{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | A32 (Base) | Performs bitwise OR. |
| orr.w | ORR.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit OR. |
| orv | ORV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | ORs all active elements into a scalar. |
| pacda | PACDA <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Signs a data pointer using Key A. |
| pacda | PACDA <Xd>, <Xn> | Data Processing | PAC (Security) | Signs a data address using Key A. |
| pacdb | PACDB <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Signs a data pointer using Key B. |
| pacdb | PACDB <Xd>, <Xn> | Data Processing | PAC (Security) | Signs a data address using Key B. |
| pacga | PACGA <Xd>, <Xn>, <Xm> | Data Processing | PAC (Security) | Computes a pointer authentication code for an address and modifier. |
| pacia | PACIA <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Signs a pointer in Xd using Key A and modifier Xm (or SP). |
| pacia | PACIA <Xd>, <Xn> | Data Processing | PAC (Security) | Signs an instruction address using Key A. |
| pacib | PACIB <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Signs a pointer in Xd using Key B. |
| pacib | PACIB <Xd>, <Xn> | Data Processing | PAC (Security) | Signs an instruction address using Key B. |
| pfalse | PFALSE <Pd>.B | SVE Predicate | SVE | Clears all elements of the predicate register. |
| pfirst | PFIRST <Pd>.B, <Pg>, <Pn>.B | SVE Predicate | SVE | Sets destination predicate to true only at the first active element. |
| pkhbt | PKHBT<c> <Rd>, <Rn>, <Rm> {, LSL #<imm>} | Data Proc | A32 (DSP) | Combines bottom half of Rn with top half of shifted Rm. |
| pkhtb | PKHTB<c> <Rd>, <Rn>, <Rm> {, ASR #<imm>} | Data Proc | A32 (DSP) | Combines top half of Rn with bottom half of shifted Rm. |
| pld | PLD [<Rn>, #<imm>] | Load/Store | A32 (System) | Hints memory system to bring data into cache. |
| pldw | PLDW [<Rn>, #<imm>] | Load/Store | A32 (Base) | Hints memory system to bring data into cache for writing. |
| pldw | PLDW [<Rn>, #<imm>] | Thumb Load/Store | T32 (Thumb2) | Hints memory system to bring data into cache for writing (Thumb). |
| pli | PLI [<Rn>, #<imm>] | Load/Store | A32 (System) | Hints memory system to bring instructions into cache. |
| pmul | PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Performs polynomial multiplication over {0,1}. |
| pmull | PMULL <Vd>.1Q, <Vn>.1D, <Vm>.1D | Crypto | Crypto (AES) | Polynomial multiply long (NEON). |
| pmull | PMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (Crypto/SIMD) | Performs polynomial multiplication over {0,1} producing wide result (Used for GCM). |
| pnext | PNEXT <Pdn>.<T>, <Pg>, <Pdn>.<T> | SVE Predicate | SVE | Finds the next active predicate bit. |
| pop | POP <registers> | Thumb Load Multiple | A32 (Base) | Pop registers from stack (Thumb 16-bit). |
| pop | POP<c> <registers> | Load Multiple | A32 (Base) | Loads registers from stack (Alias for LDMIA SP!). |
| pop.w | POP.W <registers> | Thumb Load Multiple | T32 (Thumb2) | Thumb-2 32-bit Pop. |
| prfm | PRFM <prfop>, [<Xn|SP>, #<pimm>] | Load/Store Imm | Base | Signals the memory system to prefetch data into cache. |
| prfm | PRFM <prfop>, <label> | Load Literal | Base | Prefetches data from a PC-relative address. |
| prfm | PRFM <prfop>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store Reg | Base | Prefetches data using a register offset. |
| psb | PSB CSYNC | System Alias | Profiling | Synchronizes the statistical profiling unit. |
| pssbb | PSSBB | System Hint | A32 (v8.0) | Prevents speculation on physical resources (v8.0). |
| pssbb | PSSBB | System Hint | Base (v8.5) | Prevents speculation on physical resources. |
| ptest | PTEST <Pg>, <Pn>.B | SVE Predicate | SVE | Updates processor flags (NZCV) based on predicate state. |
| ptrue | PTRUE <Pd>.<T> {, <pattern>} | SVE Predicate | SVE | Sets elements of the predicate register to true (all active). |
| push | PUSH <registers> | Thumb Store Multiple | A32 (Base) | Push registers to stack (Thumb 16-bit). |
| push | PUSH<c> <registers> | Store Multiple | A32 (Base) | Stores registers to stack (Alias for STMDB SP!). |
| push.w | PUSH.W <registers> | Thumb Store Multiple | T32 (Thumb2) | Thumb-2 32-bit Push. |
| qadd | QADD<c> <Rd>, <Rm>, <Rn> | Data Proc | A32 (Sat) | Adds two values and saturates the result. |
| qadd16 | QADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel saturating add of 2 signed halfwords. |
| qadd8 | QADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel saturating add of 4 signed bytes. |
| qdadd | QDADD<c> <Rd>, <Rm>, <Rn> | Data Proc | A32 (Sat) | Doubles the second operand, adds to first, and saturates. |
| qdsub | QDSUB<c> <Rd>, <Rm>, <Rn> | Data Proc | A32 (Sat) | Doubles the second operand, subtracts from first, and saturates. |
| qsub | QSUB<c> <Rd>, <Rm>, <Rn> | Data Proc | A32 (Sat) | Subtracts two values and saturates the result. |
| qsub16 | QSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel saturating subtract of 2 signed halfwords. |
| qsub8 | QSUB8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel saturating subtract of 4 signed bytes. |
| rbit | RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T> | SVE Permute | SVE | Reverses bits in each element. |
| rbit | RBIT <Wd>, <Wn> | Data Processing | Base | Reverses the bit order in a register. |
| rbit | RBIT <Rd>, <Rm> | Thumb Misc | A32 (Base) | Reverses bits in a 32-bit register. |
| rbit | RBIT <Xd>, <Xn> | Data Processing | Base | Reverses the bit order in a 64-bit register. |
| rbit | RBIT<c> <Rd>, <Rm> | Data Proc | A32 (Base) | Reverses bits in a 32-bit register. |
| rcw | RCW <Xt>, <Xt+1>, [<Xn>] | Atomic | FEAT_THE | Atomically updates a 128-bit descriptor in memory (Translation Hardening). |
| rcw | RCW <Xt>, <Xt+1>, [<Xn>] | Atomic | FEAT_THE (Hardening) | Atomically reads, checks, and updates a 128-bit descriptor in memory (Translation Hardening). |
| rcwa | RCWA <Xt>, <Xt+1>, [<Xn>] | Atomic | FEAT_THE (Hardening) | Read Check Write with Acquire semantics. |
| rcwal | RCWAL <Xt>, <Xt+1>, [<Xn>] | Atomic | FEAT_THE (Hardening) | Read Check Write with Acquire and Release semantics. |
| rcws | RCWS <Xt>, <Xt+1>, [<Xn>] | Atomic | FEAT_THE (Hardening) | Read Check Write with soft failure reporting (Translation Hardening). |
| ret | RET {<Xn>} | Branch | Base | Branches to address in LR (or specified register). |
| rev | REV <Zd>.<T>, <Zn>.<T> | SVE Permute | SVE | Reverses the order of elements in the vector. |
| rev | REV <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Endian swap (Thumb). |
| rev | REV <Wd>, <Wn> | Data Processing | Base | Reverses byte order (Endian swap) in a 32-bit register. |
| rev | REV <Xd>, <Xn> | Data Processing | Base | Reverses byte order in a 64-bit register. |
| rev | REV <Rd>, <Rm> | Thumb Misc | A32 (Base) | Reverses bytes (Endian swap). |
| rev | REV <Wd>, <Wn> | Data Processing | Base | Reverses the byte order in a 32-bit register (Endianness swap). |
| rev | REV<c> <Rd>, <Rm> | Data Proc | A32 (Base) | Reverses bytes (Endian swap). |
| rev16 | REV16 <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Reverse bytes in halfwords (Thumb). |
| rev16 | REV16 <Wd>, <Wn> | Data Processing | Base | Reverses bytes in each 16-bit halfword. |
| rev16 | REV16 <Rd>, <Rm> | Thumb Misc | A32 (Base) | Reverses bytes in each 16-bit halfword. |
| rev32 | REV32 <Xd>, <Xn> | Data Processing | Base | Reverses bytes in each 32-bit word (64-bit op). |
| revb | REVB <Zd>.<T>, <Pg>/M, <Zn>.<T> | SVE Permute | SVE | Reverses bytes within 16/32/64-bit elements. |
| revh | REVH <Zd>.<T>, <Pg>/M, <Zn>.<T> | SVE Permute | SVE | Reverses halfwords within 32/64-bit elements. |
| revsh | REVSH <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Reverse bytes in low halfword, sign extend (Thumb). |
| revsh | REVSH <Rd>, <Rm> | Thumb Misc | A32 (Base) | Reverses bytes in low halfword and sign-extends. |
| revw | REVW <Zd>.D, <Pg>/M, <Zn>.D | SVE Permute | SVE | Reverses words within 64-bit elements. |
| rfe | RFE<c> <Rn>{!} | System | A32 (System) | Loads PC and CPSR from the stack. |
| rmif | RMIF <Xn>, #<shift>, #<mask> | Data Processing | FEAT_FlagM | Rotates a register and inserts bits into the Process State flags. |
| rndr | RNDR <Xt> | System | FEAT_RNG | Reads a random number from hardware entropy source. |
| rndrrs | RNDRRS <Xt> | System | FEAT_RNG | Reads a random number and requests reseed. |
| ror | ROR{S}<c> <Rd>, <Rm>, <Rs> | Data Proc | A32 (Base) | Rotates register right. |
| rorv | RORV <Wd>, <Wn>, <Wm> | Data Processing | Base | Rotates register right by variable amount. |
| rrx | RRX{S}<c> <Rd>, <Rm> | Data Proc | A32 (Base) | Shifts register right by 1, inserting Carry flag into MSB. |
| rrx | RRX{S}.W <Rd>, <Rm> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Rotate Right with Extend. |
| rsb | RSB <Rd>, <Rn>, #0 | Thumb Data Proc | T32 (Thumb) | Reverse Subtract (Thumb 16-bit). |
| rsb | RSB{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | A32 (Base) | Calculates Rd = Operand2 - Rn. |
| rsb.w | RSB.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit reverse subtract. |
| rsc | RSC{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | A32 (Base) | Calculates Rd = Operand2 - Rn - NOT(Carry). |
| sadd16 | SADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel add of two signed 16-bit halfwords. |
| sadd8 | SADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel add of four signed 8-bit bytes. |
| saddl | SADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Adds lower/upper halves of signed vectors, producing wider result (Widening). |
| saddv | SADDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Sums all active signed elements into a scalar result. |
| saddw | SADDW <Vd>.<Td>, <Vn>.<Td>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Adds a wide vector to the lower/upper half of a narrow vector. |
| sb | SB | System Hint | A32 (v8.0) | Prevents speculative execution across the barrier (v8.0). |
| sb | SB | System Hint | Base (v8.0+) | Prevents speculative execution across the barrier. |
| sbc | SBC <Wd>, <Wn>, <Wm> | Data Processing | Base | Subtracts with borrow (Carry - 1). |
| sbc | SBC{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | A32 (Base) | Calculates Rd = Rn - Operand2 - NOT(Carry). |
| sbc.w | SBC.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit subtract with carry. |
| sbcs | SBCS <Wd>, <Wn>, <Wm> | Data Processing | Base | Subtracts with borrow and updates flags. |
| sbfm | SBFM <Wd>, <Wn>, #<immr>, #<imms> | Bitfield | Base | Extracts/Inserts bitfield with sign extension. |
| sbfx | SBFX<c> <Rd>, <Rn>, #<lsb>, #<width> | Data Proc | A32 (Base) | Extracts bits from a register and sign-extends them. |
| sbfx | SBFX <Rd>, <Rn>, #<lsb>, #<width> | Thumb Bitfield | A32 (Base) | Extracts and sign-extends bits. |
| scvtf | SCVTF <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE | Converts signed integers to floats. |
| scvtf | SCVTF <Hd|Sd|Dd>, <Wn|Xn> {, #<fbits>} | FP Conversion | Floating Point | Converts signed integer (GPR) to floating-point. |
| scvtf | SCVTF <Dd>, <Xn> | Float Conversion | F.P. | Converts signed integer (scalar) to floating-point. |
| sdiv | SDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Divides signed integers. |
| sdiv | SDIV <Wd>, <Wn>, <Wm> | Data Processing | Base | Divides two signed registers. |
| sdiv | SDIV <Rd>, <Rn>, <Rm> | Thumb Div | A32 (Base) | Signed integer division. |
| sdiv | SDIV<c> <Rd>, <Rn>, <Rm> | Data Proc | A32 (Base) | Signed integer division. |
| sdot | SDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> | SVE Dot Product | SVE | Computes dot product of signed integers (AI Acceleration). |
| sdot | SDOT<c>.S8 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (DotProd) | Signed Dot Product (vector by vector). |
| sdot | SDOT <Vd>.4S, <Vn>.16B, <Vm>.16B | NEON DotProd | FEAT_DotProd | Dot product of signed integers (AArch64 NEON). |
| sdot | SDOT { <Zd1>.S-<Zd2>.S }, <Zn>.B, <Zm>.B | SME2 DotProd | SME2 | Multi-vector signed dot product (SME2). |
| sel | SEL <Zd>.<T>, <Pg>, <Zn>.<T>, <Zm>.<T> | SVE Select | SVE | Selects elements from Zn or Zm based on predicate. |
| sel | SEL<c> <Rd>, <Rn>, <Rm> | Data Proc | A32 (DSP) | Selects bytes from Rn or Rm based on GE flags. |
| setend | SETEND <endian> | System | A32 (System) | Sets the endianness for data accesses (BE/LE). |
| setend | SETEND <endian> | Thumb System | A32 (System) | Set endianness (Thumb). |
| setf16 | SETF16 <Wn> | System | FEAT_FlagM | Sets PSTATE flags based on 16-bit operand. |
| setf8 | SETF8 <Wn> | System | FEAT_FlagM | Sets PSTATE flags based on 8-bit operand. |
| setpan | SETPAN #<imm> | System | A32 (System) | Enables/Disables PAN (Prevents kernel accessing user memory). |
| sev | SEV | System Alias | Base | Sends an event to all processors in the cluster (wakes up WFE). |
| sev | SEV | System Hint | A32 (Base) | Sends an event to all processors. |
| sev | SEV | Thumb System | A32 (Base) | Send event (Thumb). |
| sevl | SEVL | System Alias | Base | Sends an event locally to the executing processor. |
| sevl | SEVL | System Hint | A32 (Base) | Sends an event locally. |
| sevl | SEVL | Thumb System | A32 (Base) | Send local event (Thumb). |
| sha1c | SHA1C.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA1 hash update (Choose). |
| sha1c | SHA1C <Qd>, <Sn>, <Vm>.4S | Crypto | Crypto | SHA1 hash choose (AArch64 NEON). |
| sha1c | SHA1C <Qd>, <Sn>, <Vm>.<T> | Crypto | Crypto | SHA1 hash update (Choose function). |
| sha1h | SHA1H.32 <Qd>, <Qm> | Crypto 2-Reg | Crypto | Updates SHA1 hash state. |
| sha1h | SHA1H <Sd>, <Sn> | Crypto | Crypto | SHA1 hash update (AArch64 NEON). |
| sha1m | SHA1M.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA1 hash update (Majority). |
| sha1m | SHA1M <Qd>, <Sn>, <Vm>.<T> | Crypto | Crypto | SHA1 hash update (Majority function). |
| sha1p | SHA1P.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA1 hash update (Parity). |
| sha1p | SHA1P <Qd>, <Sn>, <Vm>.<T> | Crypto | Crypto | SHA1 hash update (Parity function). |
| sha256h | SHA256H.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA256 hash update (part 1). |
| sha256h | SHA256H <Qd>, <Qn>, <Vm>.4S | Crypto | Crypto | SHA256 hash part 1 (AArch64 NEON). |
| sha256h | SHA256H <Qd>, <Qn>, <Vm>.<T> | Crypto | Crypto | SHA256 hash update (part 1). |
| sha256h2 | SHA256H2.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA256 hash update (part 2). |
| sha256h2 | SHA256H2 <Qd>, <Qn>, <Vm>.4S | Crypto | Crypto | SHA256 hash part 2 (AArch64 NEON). |
| sha256h2 | SHA256H2 <Qd>, <Qn>, <Vm>.<T> | Crypto | Crypto | SHA256 hash update (part 2). |
| sha256su0 | SHA256SU0.32 <Qd>, <Qm> | Crypto 2-Reg | Crypto | SHA256 schedule update instruction 0. |
| sha256su1 | SHA256SU1.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto | SHA256 schedule update instruction 1. |
| sha512h | SHA512H.64 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SHA512) | SHA512 hash update part 1. |
| sha512h2 | SHA512H2.64 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SHA512) | SHA512 hash update part 2. |
| sha512su0 | SHA512SU0.64 <Qd>, <Qm> | Crypto 2-Reg | Crypto (SHA512) | SHA512 schedule update instruction 0. |
| sha512su1 | SHA512SU1.64 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SHA512) | SHA512 schedule update instruction 1. |
| shadd16 | SHADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Signed add and halving (average) of 2 halfwords. |
| shadd8 | SHADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Signed add and halving (average) of 4 bytes. |
| shl | SHL <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts elements left by immediate value. |
| shll | SHLL <Vd>.<Td>, <Vn>.<Ts>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts narrow vector left, extending to wide result. |
| shrn | SHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts wide vector right, narrowing to destination (Upper/Lower). |
| shsub16 | SHSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Signed subtract and halving of 2 halfwords. |
| shsub8 | SHSUB8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Signed subtract and halving of 4 bytes. |
| sli | SLI <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts source left and inserts into destination. |
| sm3partw1 | SM3PARTW1.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SM3) | SM3 schedule update part 1. |
| sm3partw2 | SM3PARTW2.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SM3) | SM3 schedule update part 2. |
| sm3ss1 | SM3SS1.32 <Qd>, <Qn>, <Qm> | Crypto 3-Reg | Crypto (SM3) | SM3 cryptographic hash step 1. |
| sm3tt1a | SM3TT1A.32 <Qd>, <Dn>, <Dm>, #<imm> | Crypto Imm | Crypto (SM3) | SM3 cryptographic hash step 2A. |
| sm3tt1b | SM3TT1B.32 <Qd>, <Dn>, <Dm>, #<imm> | Crypto Imm | Crypto (SM3) | SM3 cryptographic hash step 2B. |
| sm3tt2a | SM3TT2A.32 <Qd>, <Dn>, <Dm>, #<imm> | Crypto Imm | Crypto (SM3) | SM3 cryptographic hash step 3A. |
| sm3tt2b | SM3TT2B.32 <Qd>, <Dn>, <Dm>, #<imm> | Crypto Imm | Crypto (SM3) | SM3 cryptographic hash step 3B. |
| sm4e | SM4E.32 <Qd>, <Qm> | Crypto 2-Reg | Crypto (SM4) | SM4 encryption step. |
| sm4ekey | SM4EKEY.32 <Qd>, <Qm> | Crypto 2-Reg | Crypto (SM4) | SM4 key schedule step. |
| smaddl | SMADDL <Xd>, <Wn>, <Wm>, <Xa> | Data Processing | Base | Multiplies two 32-bit registers, adds to 64-bit register (64-bit result). |
| smax | SMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Determines maximum signed value per element. |
| smax | SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Returns larger signed integer per element. |
| smaxv | SMAXV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds max signed element in vector. |
| smaxv | SMAXV <V><d>, <Vn>.<T> | SIMD Across Lane | NEON (SIMD) | Finds the maximum signed value across the vector. |
| smc | SMC<c> #<imm> | System | A32 (System) | Calls the Secure Monitor (EL3). |
| smc | SMC #<imm> | Thumb System | A32 (Security) | Calls the Secure Monitor (EL3) from Thumb state. |
| smin | SMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Determines minimum signed value per element. |
| smin | SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Returns smaller signed integer per element. |
| sminv | SMINV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds min signed element in vector. |
| smlabb | SMLABB<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Accumulates (Rn.B * Rm.B) into Ra. |
| smlabt | SMLABT<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Accumulates (Rn.B * Rm.T) into Ra. |
| smlad | SMLAD{X}<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Dual multiply add + accumulate. |
| smlal | SMLAL <RdLo>, <RdHi>, <Rn>, <Rm> | Thumb Mul | A32 (Base) | Signed Multiply Accumulate (64-bit result). |
| smlal | SMLAL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Multiplies signed narrow vectors and adds to wide destination. |
| smlalbb | SMLALBB<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Accumulates (Rn.B * Rm.B) into 64-bit pair. |
| smlalbt | SMLALBT<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Accumulates (Rn.B * Rm.T) into 64-bit pair. |
| smlald | SMLALD{X}<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Dual multiply add + 64-bit accumulate. |
| smlaltb | SMLALTB<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Accumulates (Rn.T * Rm.B) into 64-bit pair. |
| smlaltt | SMLALTT<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Accumulates (Rn.T * Rm.T) into 64-bit pair. |
| smlatb | SMLATB<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Accumulates (Rn.T * Rm.B) into Ra. |
| smlatt | SMLATT<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Accumulates (Rn.T * Rm.T) into Ra. |
| smlawb | SMLAWB<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Performs SMULWB and adds to accumulator. |
| smlawt | SMLAWT<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Performs SMULWT and adds to accumulator. |
| smlsd | SMLSD{X}<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | Dual multiply subtract + accumulate. |
| smlsld | SMLSLD{X}<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Dual multiply subtract + 64-bit accumulate. |
| smmla | SMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_I8MM (AI) | Performs 2x2 matrix multiplication on Signed Int8 tiles. |
| smmla | SMMLA{R}<c> <Rd>, <Rn>, <Rm>, <Ra> | Multiply | A32 (DSP) | SMMUL + Accumulate. |
| smmul | SMMUL{R}<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies and returns the top 32-bits of the 64-bit result. |
| smsubl | SMSUBL <Xd>, <Wn>, <Wm>, <Xa> | Data Processing | Base | Calculates (Xa - (Wn * Wm)) (64-bit result). |
| smuad | SMUAD{X}<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Performs two 16x16 multiplies and adds results (Top*Top + Bot*Bot). |
| smulbb | SMULBB<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies bottom 16 bits of Rn and Rm. |
| smulbt | SMULBT<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies bottom 16 bits of Rn and top 16 bits of Rm. |
| smulh | SMULH <Xd>, <Xn>, <Xm> | Data Processing | Base | Multiplies two 64-bit registers, keeps high 64 bits. |
| smull | SMULL <RdLo>, <RdHi>, <Rn>, <Rm> | Thumb Mul | A32 (Base) | Signed Multiply (64-bit result). |
| smull | SMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Multiplies signed narrow vectors, producing wider result. |
| smultb | SMULTB<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies top 16 bits of Rn and bottom 16 bits of Rm. |
| smultt | SMULTT<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies top 16 bits of Rn and top 16 bits of Rm. |
| smulwb | SMULWB<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies 32-bit Rn by bottom 16-bits of Rm, takes top 32-bits of result. |
| smulwt | SMULWT<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Multiplies 32-bit Rn by top 16-bits of Rm, takes top 32-bits of result. |
| smusd | SMUSD{X}<c> <Rd>, <Rn>, <Rm> | Multiply | A32 (DSP) | Performs two 16x16 multiplies and subtracts results. |
| splice | SPLICE <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T> | SVE Permute | SVE | Splices two vectors based on the last active element of the first. |
| sqadd | SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds signed integers with saturation. |
| sqsub | SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Subtracts signed integers with saturation. |
| sqxtn | SQXTN <Vd>.<Tb>, <Vn>.<Ta> | SIMD Shift Imm | NEON (SIMD) | Reads wide elements, saturates, and narrows. |
| sri | SRI <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts source right and inserts into destination. |
| srs | SRS<c> SP{!}, #<mode> | System | A32 (System) | Stores LR and SPSR to the stack of a specific mode. |
| ssat | SSAT<c> <Rd>, #<imm>, <Rm> {, <shift>} | Data Proc | A32 (DSP) | Saturates a signed value to a specified bit width. |
| ssat16 | SSAT16<c> <Rd>, #<imm>, <Rm> | Data Proc | A32 (DSP) | Saturates two signed 16-bit values. |
| ssbb | SSBB | System Hint | A32 (v8.0) | Prevents speculative loads bypassing earlier stores (v8.0). |
| sshr | SSHR <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts elements right (arithmetic/sign-extending). |
| ssra | SSRA <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Arithmetic right shift and add to destination. |
| ssub16 | SSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel sub of two signed 16-bit halfwords. |
| ssubl | SSUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Subtracts signed narrow vectors, producing wider result. |
| st1 | ST1 { <Vt>.<T>, ... }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Stores one element structure from 1-4 registers to memory. |
| st1b | ST1B { <Zt>.B }, <Pg>, [<Xn|SP>] | SVE Store | SVE | Stores active bytes from vector to memory. |
| st1d | ST1D { <Zt>.D }, <Pg>, [<Xn|SP>] | SVE Store | SVE | Stores active doublewords from vector to memory. |
| st1h | ST1H { <Zt>.H }, <Pg>, [<Xn|SP>] | SVE Store | SVE | Stores active halfwords from vector to memory. |
| st1w | ST1W { <Zt>.S }, <Pg>, [<Xn|SP>] | SVE Store | SVE | Stores active words from vector to memory. |
| st1w | ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, SXTW #<shift>] | SVE Scatter | SVE | Stores words to non-contiguous addresses. |
| st2 | ST2 { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Stores two-element structures from two registers to memory (Interleave). |
| st2g | ST2G <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores Allocation Tags to two granules. |
| st2g | ST2G <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores the Allocation Tag to two memory granules. |
| st3 | ST3 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Stores three-element structures from three registers (Interleave RGB). |
| st4 | ST4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] | SIMD Load/Store | NEON (SIMD) | Stores four-element structures from four registers (Interleave RGBA). |
| st64b | ST64B <Xt>, [<Xn|SP>] | Load/Store | LSE (Atomics) | Stores a 64-byte block of data atomically. |
| st64bv | ST64BV <Ws>, <Xt>, [<Xn|SP>] | Load/Store | LSE (Atomics) | Stores 64 bytes atomically and returns status (Success/Fail). |
| st64bv0 | ST64BV0 <Ws>, <Xt>, [<Xn|SP>] | Load/Store | LSE (Atomics) | Stores 64 bytes (eliding the first 8 bytes as zero) and returns status. |
| stc | STC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | A32 (System) | Stores coprocessor contents to memory. |
| stc2 | STC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} | Coprocessor | A32 (System) | Stores coprocessor contents to memory (Extension encoding). |
| stg | STG <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores the Allocation Tag to memory. |
| stg | STG <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores the Allocation Tag to memory. |
| stgp | STGP <Xt>, <Xt2>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores Tag and two 64-bit data values. |
| stl | STL<c> <Rt>, [<Rn>] | Load/Store | A32 (Atomic) | Stores a word with Release semantics. |
| stlex | STLEX<c> <Rd>, <Rt>, [<Rn>] | Load/Store | A32 (Atomic) | Stores a word with Release Exclusive semantics. |
| stlexb | STLEXB<c> <Rd>, <Rt>, [<Rn>] | Store Excl | A32 (Atomic) | Stores a byte with Release semantics if exclusive. |
| stlexd | STLEXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>] | Store Excl | A32 (Atomic) | Stores a doubleword with Release semantics if exclusive. |
| stlexh | STLEXH<c> <Rd>, <Rt>, [<Rn>] | Store Excl | A32 (Atomic) | Stores a halfword with Release semantics if exclusive. |
| stlr | STLR <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Stores a word with Release semantics. |
| stlrb | STLRB <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Stores a byte with Release semantics. |
| stlrh | STLRH <Wt>, [<Xn|SP>] | Load/Store | Base (Atomic) | Stores a halfword with Release semantics. |
| stlxr | STLXR <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a word with Release Exclusive semantics. |
| stlxrb | STLXRB <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a byte with Release Exclusive semantics. |
| stlxrh | STLXRH <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a halfword with Release Exclusive semantics. |
| stm | STM <Rn>!, <registers> | Thumb Store Multiple | A32 (Base) | Store multiple registers (Thumb 16-bit). |
| stm | STM<mode><c> <Rn>{!}, <registers> | Store Multiple | A32 (Base) | Stores multiple registers to memory. |
| stm.w | STM.W <Rn>{!}, <registers> | Thumb Store Multiple | T32 (Thumb2) | Thumb-2 32-bit Store Multiple. |
| stnp | STNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Base | Stores two registers, hinting non-temporal data. |
| stp | STP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Floating Point | Stores two floating-point/SIMD registers. |
| stp | STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Base | Stores two 32-bit registers. |
| stp | STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Base | Stores two 64-bit registers. |
| str | STR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>] | Load/Store | Floating Point | Stores a floating-point/SIMD register to memory. |
| str | STR <Wt>, [<Xn|SP>, #<pimm>] | Load/Store Imm | Base | Stores a register to memory (Immediate offset). |
| str | STR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store Reg | Base | Stores a register to memory (Register offset). |
| str | STR<c> <Rt>, [<Rn>, #+/-<imm>]{!} | Load/Store | A32 (Base) | Stores a word to memory. |
| str.w | STR.W <Rt>, [<Rn>, #<imm>] | Thumb Store | T32 (Thumb2) | Thumb-2 32-bit Store Word. |
| strb | STRB <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Stores the low byte of a register. |
| strb | STRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Base | Stores the low byte of a register using register offset. |
| strb.w | STRB.W <Rt>, [<Rn>, #<imm>] | Thumb Store | T32 (Thumb2) | Thumb-2 32-bit Store Byte. |
| strbt | STRBT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Stores a byte using User Mode permissions. |
| strd | STRD <Rt>, <Rt2>, [<Rn>, #+/-<imm>] | Thumb Store | A32 (Base) | Stores two words to memory (Thumb). |
| strex | STREX <Rd>, <Rt>, [<Rn>] | Thumb Store Excl | A32 (Atomic) | Stores word if exclusive monitor is open (Thumb). |
| strexb | STREXB<c> <Rd>, <Rt>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Stores a byte if address is still exclusive. |
| strexb | STREXB <Rd>, <Rt>, [<Rn>] | Thumb Store Excl | A32 (Atomic) | Stores byte exclusively (Thumb). |
| strexd | STREXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Stores a doubleword if address is still exclusive. |
| strexh | STREXH<c> <Rd>, <Rt>, [<Rn>] | Load/Store Excl | A32 (Atomic) | Stores a halfword if address is still exclusive. |
| strexh | STREXH <Rd>, <Rt>, [<Rn>] | Thumb Store Excl | A32 (Atomic) | Stores halfword exclusively (Thumb). |
| strh | STRH <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Base | Stores the low halfword of a register. |
| strh | STRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Base | Stores the low halfword of a register using register offset. |
| strh.w | STRH.W <Rt>, [<Rn>, #<imm>] | Thumb Store | T32 (Thumb2) | Thumb-2 32-bit Store Halfword. |
| strht | STRHT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Stores a halfword using User Mode permissions. |
| strt | STRT<c> <Rt>, [<Rn>, #+/-<imm>] | Load/Store | A32 (Base) | Stores a word using User Mode permissions. |
| sttr | STTR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a register as if in EL0 (User mode). |
| sttrb | STTRB <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a byte as if in EL0. |
| sttrh | STTRH <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a halfword as if in EL0. |
| stur | STUR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a register using an unscaled immediate offset. |
| sturb | STURB <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a byte using an unscaled immediate offset. |
| sturh | STURH <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Base | Stores a halfword using an unscaled immediate offset. |
| stxp | STXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores two registers if exclusive monitor matches. |
| stxr | STXR <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a word if exclusive monitor matches. |
| stxrb | STXRB <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a byte if exclusive monitor matches. |
| stxrh | STXRH <Ws>, <Wt>, [<Xn|SP>] | Load/Store Excl | Base (Atomic) | Stores a halfword if exclusive monitor matches. |
| stz2g | STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores Allocation Tags and zeros two granules. |
| stz2g | STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores Tag and zeros memory for two granules. |
| stzg | STZG <Xt|SP>, [<Xn|SP>, #<simm>] | Load/Store | MTE (Memory Tagging) | Stores the Allocation Tag and zeros the data granule. |
| sub | SUB <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing | Base | Subtracts extended register from register. |
| sub | SUB <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing | Base | Subtracts immediate from register. |
| sub | SUB <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing | Base | Subtracts shifted register from register. |
| sub | SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Subtracts elements of Vm from Vn. |
| sub | SUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Subtracts vector Zm from Zdn under predicate. |
| sub | SUB{S}<c> <Rd>, <Rn>, <Operand2> | Data Proc | A32 (Base) | Subtracts two values. |
| sub.w | SUB.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit subtract. |
| subg | SUBG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> | Data Processing | MTE (Memory Tagging) | Subtracts an immediate from an address, modifying the Allocation Tag (MTE). |
| subp | SUBP <Xd>, <Xn|SP>, <Xm|SP> | Data Processing | MTE (Memory Tagging) | Subtracts pointers ignoring Tags. |
| subp | SUBP <Xd>, <Xn|SP>, <Xm|SP> | Data Processing | MTE (Memory Tagging) | Subtracts pointers (ignoring tags) to get difference. |
| subs | SUBS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing | Base | Subtracts extended register and updates flags. |
| subs | SUBS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing | Base | Subtracts immediate and updates flags. |
| subs | SUBS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing | Base | Subtracts shifted register and updates flags. |
| subs | SUBS PC, LR, #<imm> | Data Proc | A32 (Base) | Subs PC, LR, #imm (Exception return mechanism). |
| subs | SUBS PC, LR, #<imm> | Thumb Data Proc | A32 (Base) | Subs PC, LR, #imm (Exception return mechanism). |
| sudot | SUDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>[<index>] | NEON 3-Reg | FEAT_I8MM (AI) | Dot product of Signed Int8 and Unsigned Int8 (Indexed). |
| sunpkhi | SUNPKHI <Zd>.<T>, <Zn>.<Tb> | SVE Permute | SVE | Unpacks and sign-extends upper half of vector elements. |
| sunpklo | SUNPKLO <Zd>.<T>, <Zn>.<Tb> | SVE Permute | SVE | Unpacks and sign-extends lower half of vector elements. |
| svc | SVC #<imm> | Exception | System | Causes a Supervisor Call exception (to EL1). |
| svc | SVC #<imm> | Thumb System | T32 (Thumb) | System Call (Thumb encoding). |
| svc | SVC<c> #<imm> | System | A32 (System) | System call (formerly SWI). |
| swp | SWP <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic swap of a word. |
| swp | SWP<c> <Rt>, <Rt2>, [<Rn>] | Load/Store | A32 (Atomic) | Atomic swap word (Legacy). |
| sxtab | SXTAB<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Sign-extends a byte from Rm and adds to Rn. |
| sxtab16 | SXTAB16<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Sign-extends two bytes and adds to two halfwords. |
| sxtah | SXTAH<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Sign-extends a halfword and adds to Rn. |
| sxtb | SXTB <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Sign-extends byte to word (Thumb). |
| sxtb | SXTB<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (Base) | Sign-extends the low byte (8-bits) to 32-bits. |
| sxtb | SXTB <Wd>, <Wn> | Bitfield | Base | Extracts the lowest 8 bits and sign-extends to 32 bits (Alias for SBFM). |
| sxtb16 | SXTB16<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Sign-extends two bytes to two halfwords. |
| sxth | SXTH <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Sign-extends halfword to word (Thumb). |
| sxth | SXTH<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (Base) | Sign-extends the low halfword (16-bits) to 32-bits. |
| sxtw | SXTW <Xd>, <Wn> | Bitfield | Base | Sign-extends a 32-bit register to 64 bits (Alias for SBFM). |
| sys | SYS #<op1>, Cn, Cm, #<op2> {, <Xt>} | System | System | Executes a system instruction (cache/TLB maintenance). |
| tbb | TBB [<Rn>, <Rm>] | Thumb Branch | T32 (Thumb) | PC-relative branch using a table of bytes (Switch statements). |
| tbh | TBH [<Rn>, <Rm>, LSL #1] | Thumb Branch | T32 (Thumb) | PC-relative branch using a table of halfwords. |
| tbl | TBL <Vd>.<T>, { <Vn>.16B, ... }, <Vm>.<T> | SIMD Table | NEON (SIMD) | Look up elements in a table of vectors using indices. |
| tbl | TBL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Looks up elements in a vector table using indices. |
| tbnz | TBNZ <Wt|Xt>, #<imm>, <label> | Branch | Base | Branches if specified bit is 1. |
| tbz | TBZ <Wt|Xt>, #<imm>, <label> | Branch | Base | Branches if specified bit is 0. |
| tcommit | TCOMMIT | System | TME (Transactional) | Commits the current transaction. |
| teq | TEQ<c> <Rn>, <Operand2> | Data Proc | A32 (Base) | Bitwise Exclusive OR and update flags (discard result). |
| teq.w | TEQ.W <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Test Equivalence (XOR and update flags). |
| tlbi | TLBI VMALLE1IS | System | Base (System) | Invalidates all TLB entries in the inner shareable domain. |
| tlbi | TLBI VAE1, <Xt> | System | Base (System) | Invalidates TLB entries by Virtual Address. |
| tlbi | TLBI <op> {, <Xt>} | System Alias | System | Invalidates Translation Lookaside Buffer entries. |
| trcit | TRCIT <Xt> | System | Trace | Generates a trace packet. |
| trn1 | TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | Transposes elements (Lower). |
| trn1 | TRN1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Interleaves even elements from two vectors. |
| trn2 | TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | Transposes elements (Upper). |
| trn2 | TRN2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Interleaves odd elements from two vectors. |
| tsb | TSB CSYNC | System Hint | A32 (Trace) | Ensures trace generation is complete (v8.2). |
| tsb | TSB CSYNC | System Hint | Trace | Ensures trace generation is complete. |
| tst | TST<c> <Rn>, <Operand2> | Data Proc | A32 (Base) | Bitwise AND and update flags (discard result). |
| tst.w | TST.W <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Test (AND and update flags). |
| tstart | TSTART <Xd> | System | TME (Transactional) | Starts a memory transaction. Returns 0 if successful. |
| ttest | TTEST <Xd> | System | TME (Transactional) | Tests the transaction nesting depth. |
| uadd16 | UADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel add of two unsigned 16-bit halfwords. |
| uadd8 | UADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel add of four unsigned 8-bit bytes. |
| uaddl | UADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Adds lower/upper halves of unsigned vectors, producing wider result. |
| uaddv | UADDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Sums all active unsigned elements into a scalar result. |
| uaddw | UADDW <Vd>.<Td>, <Vn>.<Td>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Adds a wide vector to the lower/upper half of a narrow vector (Unsigned). |
| ubfm | UBFM <Wd>, <Wn>, #<immr>, #<imms> | Bitfield | Base | Extracts/Inserts bitfield (Zero Extend). |
| ubfx | UBFX<c> <Rd>, <Rn>, #<lsb>, #<width> | Data Proc | A32 (Base) | Extracts bits from a register and zero-extends them. |
| ubfx | UBFX <Rd>, <Rn>, #<lsb>, #<width> | Thumb Bitfield | A32 (Base) | Extracts and zero-extends bits. |
| ucvtf | UCVTF <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE | Converts unsigned integers to floats. |
| ucvtf | UCVTF <Hd|Sd|Dd>, <Wn|Xn> {, #<fbits>} | FP Conversion | Floating Point | Converts unsigned integer (GPR) to floating-point. |
| udf | UDF #<imm> | System | A32 (Base) | Permanently undefined instruction (generates Undefined Instruction exception). |
| udf | UDF #<imm> | Thumb System | T32 (Thumb) | Permanently undefined instruction (Thumb). |
| udiv | UDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Divides unsigned integers. |
| udiv | UDIV <Wd>, <Wn>, <Wm> | Data Processing | Base | Divides two unsigned registers. |
| udiv | UDIV <Rd>, <Rn>, <Rm> | Thumb Div | A32 (Base) | Unsigned integer division. |
| udiv | UDIV<c> <Rd>, <Rn>, <Rm> | Data Proc | A32 (Base) | Unsigned integer division. |
| udot | UDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> | SVE Dot Product | SVE | Computes dot product of unsigned integers. |
| udot | UDOT<c>.U8 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (DotProd) | Unsigned Dot Product (vector by vector). |
| udot | UDOT <Vd>.4S, <Vn>.16B, <Vm>.16B | NEON DotProd | FEAT_DotProd | Dot product of unsigned integers (AArch64 NEON). |
| udot | UDOT { <Zd1>.S-<Zd2>.S }, <Zn>.B, <Zm>.B | SME2 DotProd | SME2 | Multi-vector unsigned dot product (SME2). |
| uhadd16 | UHADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned average of 2 halfwords. |
| uhadd8 | UHADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned average of 4 bytes. |
| uhsub16 | UHSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned halving subtract of 2 halfwords. |
| uhsub8 | UHSUB8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned halving subtract of 4 bytes. |
| umaal | UMAAL<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (DSP) | Calculates (Rn * Rm) + RdLo + RdHi -> 64-bit result. |
| umaddl | UMADDL <Xd>, <Wn>, <Wm>, <Xa> | Data Processing | Base | Multiplies two 32-bit regs, adds to 64-bit reg (Unsigned). |
| umax | UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Determines maximum unsigned value per element. |
| umax | UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Returns larger unsigned integer per element. |
| umaxv | UMAXV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds max unsigned element in vector. |
| umin | UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Determines minimum unsigned value per element. |
| umin | UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Returns smaller unsigned integer per element. |
| uminv | UMINV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds min unsigned element in vector. |
| uminv | UMINV <V><d>, <Vn>.<T> | SIMD Across Lane | NEON (SIMD) | Finds the minimum unsigned value across the vector. |
| umlal | UMLAL <RdLo>, <RdHi>, <Rn>, <Rm> | Thumb Mul | A32 (Base) | Unsigned Multiply Accumulate (64-bit result). |
| umlal | UMLAL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (Base) | Unsigned (Rn * Rm) + 64-bit Accumulator. |
| umlal | UMLAL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Multiplies unsigned narrow vectors and adds to wide destination. |
| ummla | UMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_I8MM (AI) | Performs 2x2 matrix multiplication on Unsigned Int8 tiles. |
| umsubl | UMSUBL <Xd>, <Wn>, <Wm>, <Xa> | Data Processing | Base | Calculates (Xa - (Wn * Wm)) (Unsigned 64-bit). |
| umulh | UMULH <Xd>, <Xn>, <Xm> | Data Processing | Base | Multiplies two 64-bit registers, keeps high 64 bits (Unsigned). |
| umull | UMULL <RdLo>, <RdHi>, <Rn>, <Rm> | Thumb Mul | A32 (Base) | Unsigned Multiply (64-bit result). |
| umull | UMULL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm> | Multiply | A32 (Base) | Unsigned (Rn * Rm) -> 64-bit Result. |
| umull | UMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Multiplies unsigned narrow vectors, producing wider result. |
| uqadd | UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds unsigned integers with saturation. |
| uqadd16 | UQADD16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned saturating add of 2 halfwords. |
| uqadd8 | UQADD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned saturating add of 4 bytes. |
| uqsub | UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Subtracts unsigned integers with saturation. |
| uqsub16 | UQSUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned saturating subtract of 2 halfwords. |
| uqsub8 | UQSUB8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Unsigned saturating subtract of 4 bytes. |
| uqxtn | UQXTN <Vd>.<Tb>, <Vn>.<Ta> | SIMD Shift Imm | NEON (SIMD) | Reads wide unsigned elements, saturates, and narrows. |
| urecpe | URECPE <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Estimates reciprocal for unsigned integers. |
| usad8 | USAD8<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Computes sum of absolute differences of bytes (Video Codec). |
| usada8 | USADA8<c> <Rd>, <Rn>, <Rm>, <Ra> | SIMD Integer | A32 (DSP) | USAD8 plus accumulator. |
| usat | USAT<c> <Rd>, #<imm>, <Rm> {, <shift>} | Data Proc | A32 (DSP) | Saturates an unsigned value to a specified bit width. |
| usat16 | USAT16<c> <Rd>, #<imm>, <Rm> | Data Proc | A32 (DSP) | Saturates two unsigned 16-bit values. |
| usdot | USDOT<c>.S8 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (DotProd) | Dot product of unsigned and signed integers. |
| usdot | USDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_I8MM (AI) | Dot product of Unsigned Int8 and Signed Int8. |
| ushr | USHR <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Shifts elements right (logical). |
| usmmla | USMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_I8MM (AI) | Matrix multiply Unsigned Int8 with Signed Int8. |
| usra | USRA <Vd>.<T>, <Vn>.<T>, #<shift> | SIMD Shift Imm | NEON (SIMD) | Logical right shift and add to destination. |
| usub16 | USUB16<c> <Rd>, <Rn>, <Rm> | SIMD Integer | A32 (DSP) | Parallel sub of two unsigned 16-bit halfwords. |
| usubl | USUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | NEON (SIMD) | Subtracts unsigned narrow vectors, producing wider result. |
| uunpkhi | UUNPKHI <Zd>.<T>, <Zn>.<Tb> | SVE Permute | SVE | Unpacks and zero-extends upper half of vector elements. |
| uunpklo | UUNPKLO <Zd>.<T>, <Zn>.<Tb> | SVE Permute | SVE | Unpacks and zero-extends lower half of vector elements. |
| uxtab | UXTAB<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Zero-extends a byte and adds to Rn. |
| uxtab16 | UXTAB16<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Zero-extends two bytes and adds to two halfwords. |
| uxtah | UXTAH<c> <Rd>, <Rn>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Zero-extends a halfword and adds to Rn. |
| uxtb | UXTB <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Zero-extends byte to word (Thumb). |
| uxtb | UXTB<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (Base) | Zero-extends the low byte to 32-bits. |
| uxtb16 | UXTB16<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (DSP) | Zero-extends two bytes to two halfwords. |
| uxth | UXTH <Rd>, <Rm> | Thumb Data Proc | T32 (Thumb) | Zero-extends halfword to word (Thumb). |
| uxth | UXTH<c> <Rd>, <Rm> {, <rotation>} | Data Proc | A32 (Base) | Zero-extends the low halfword to 32-bits. |
| uzp1 | UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | De-interleaves lower halves (Selects odd elements). |
| uzp1 | UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Selects even elements from concatenated vectors. |
| uzp2 | UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | De-interleaves upper halves (Selects even elements). |
| uzp2 | UZP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Selects odd elements from concatenated vectors. |
| vaba | VABA<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Computes absolute difference and adds to accumulator. |
| vabal | VABAL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Computes absolute difference of narrow elements and adds to wide acc. |
| vabd | VABD<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Computes absolute difference between elements. |
| vabdl | VABDL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Computes absolute difference of narrow elements to wide result. |
| vabs | VABS<c>.F64 <Dd>, <Dm> | VFP Unary | VFP (Float) | Absolute value of double-precision register. |
| vabs | VABS<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Calculates absolute value. |
| vabs | VABS<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Calculates absolute value of integer/float elements. |
| vacge | VACGE<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Compares absolute values (|Vn| >= |Vm|). |
| vacgt | VACGT<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Compares absolute values (|Vn| > |Vm|). |
| vadd | VADD<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Adds two floating-point values. |
| vadd | VADD<c>.F64 <Dd>, <Dn>, <Dm> | VFP Arith | VFP (Float) | Adds two double-precision floating-point values. |
| vadd | VADD<c>.I<size> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Adds integer elements of two vectors. |
| vaddhn | VADDHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Adds 2N-bit elements, selects high N-bits for result. |
| vaddl | VADDL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Adds N-bit elements, producing 2N-bit results. |
| vaddw | VADDW<c>.<dt> <Qd>, <Qn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Adds N-bit vector to 2N-bit vector. |
| vand | VAND<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Bitwise AND of two vectors. |
| vbfcvt | VBFCVT<c>.BF16.F32 <Qd>, <Qm> | NEON BFloat16 | NEON (BFloat16) | Converts Float32 to BFloat16. |
| vbfdot | VBFDOT<c>.BF16 <Qd>, <Qn>, <Qm> | NEON BFloat16 | NEON (BFloat16) | BFloat16 dot product to float32 accumulator. |
| vbfmmla | VBFMMLA<c>.BF16 <Qd>, <Qn>, <Qm> | NEON BFloat16 | NEON (BFloat16) | BFloat16 matrix multiply-accumulate. |
| vbic | VBIC<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | ANDs Vd with NOT of Vm (Vd & ~Vm). |
| vbif | VBIF<c> <Qd>, <Qm>, <Qn> | NEON 3-Reg | NEON (SIMD) | Inserts bits from Vm into Vd where Vn (mask) is 0. |
| vbit | VBIT<c> <Qd>, <Qm>, <Qn> | NEON 3-Reg | NEON (SIMD) | Inserts bits from Vm into Vd where Vn (mask) is 1. |
| vbsl | VBSL<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Selects bits from Vn or Vm based on Vd (mask). |
| vcadd | VCADD<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot> | NEON Complex | NEON (Complex) | Complex integer addition with rotation (NEON). |
| vceq | VCEQ<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Sets destination bits to all 1s if elements equal, else 0s. |
| vcge | VCGE<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Compares elements (>=) and sets result mask. |
| vcgt | VCGT<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Compares elements (>) and sets result mask. |
| vcle | VCLE<c>.<dt> <Qd>, <Qn>, <Qm> | NEON Alias | NEON (SIMD) | Compares elements (<=). Alias for VCGE with swapped operands. |
| vcls | VCLS<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Counts number of consecutive sign bits. |
| vclt | VCLT<c>.<dt> <Qd>, <Qn>, <Qm> | NEON Alias | NEON (SIMD) | Compares elements (<). Alias for VCGT with swapped operands. |
| vclz | VCLZ<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Counts number of consecutive zeros. |
| vcmla | VCMLA<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot> | NEON Complex | NEON (Complex) | Complex integer multiply-accumulate with rotation. |
| vcmp | VCMP<c>.F32 <Sd>, #0.0 | VFP Compare | VFP (Float) | Compares a floating-point value with #0.0. |
| vcmp | VCMP<c>.F64 <Dd>, <Dm> | VFP Compare | VFP (Float) | Compares two double-precision values. |
| vcmp | VCMP<c>.F32 <Sd>, <Sm> | VFP Compare | VFP (Float) | Compares two floating-point values. |
| vcmpe | VCMPE<c>.F32 <Sd>, <Sm> | VFP Compare | VFP (Float) | Compares values and raises exception on NaN. |
| vcnt | VCNT<c>.8 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Population count (number of 1s) per byte. |
| vcvt | VCVT<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits> | VFP Convert | VFP (Float) | Converts between floating-point and fixed-point. |
| vcvt | VCVT<c>.<Td>.<Tm> <Sd>, <Sm> | VFP Convert | VFP (Float) | Converts float to signed/unsigned integer. |
| vcvta | VCVTA<c>.<dt>.F64 <Sd>, <Dm> | VFP Convert | VFP (Float) | Converts double to integer, rounding to nearest. |
| vcvta | VCVTA<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding to nearest. |
| vcvtb | VCVTB<c>.F16.F32 <Sd>, <Sm> | VFP Convert | VFP (Half) | Converts single-precision to half-precision (Bottom half). |
| vcvtb | VCVTB<c>.F16.F32 <Sd>, <Sm> | VFP Convert | VFP (Half) | Converts single-precision to half-precision (Bottom). |
| vcvtm | VCVTM<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding towards -Inf (Floor). |
| vcvtn | VCVTN<c>.<dt>.F64 <Sd>, <Dm> | VFP Convert | VFP (Float) | Converts double to integer, rounding to nearest even. |
| vcvtn | VCVTN<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding to nearest even. |
| vcvtp | VCVTP<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Converts float to integer, rounding towards +Inf (Ceil). |
| vcvtt | VCVTT<c>.F16.F32 <Sd>, <Sm> | VFP Convert | VFP (Half) | Converts single-precision to half-precision (Top half). |
| vcvtt | VCVTT<c>.F16.F32 <Sd>, <Sm> | VFP Convert | VFP (Half) | Converts single-precision to half-precision (Top). |
| vdiv | VDIV<c>.F64 <Dd>, <Dn>, <Dm> | VFP Arith | VFP (Float) | Divides two double-precision registers. |
| vdiv | VDIV<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Divides two floating-point values. |
| vdup | VDUP<c>.<dt> <Qd>, <Dm[x]> | NEON Scalar | NEON (SIMD) | Duplicates a scalar value to all lanes of a vector. |
| veor | VEOR<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Bitwise XOR of two vectors. |
| vext | VEXT<c>.8 <Qd>, <Qn>, <Qm>, #<imm> | NEON Extract | NEON (SIMD) | Extracts a new vector from a pair of vectors (Sliding window). |
| vfma | VFMA<c>.F64 <Qd>, <Qn>, <Qm> | VFP Arith | VFPv4 (Float) | Fused multiply-add (Double). |
| vfma | VFMA<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | VFPv4 (SIMD) | Computes Vd = Vd + (Vn * Vm) with single rounding. |
| vfms | VFMS<c>.F64 <Qd>, <Qn>, <Qm> | VFP Arith | VFPv4 (Float) | Fused multiply-subtract (Double). |
| vfms | VFMS<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | VFPv4 (SIMD) | Computes Vd = Vd - (Vn * Vm) with single rounding. |
| vfnma | VFNMA<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFPv4 (Float) | Computes Vd = Vd - (Vn * Vm). |
| vfnms | VFNMS<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFPv4 (Float) | Computes Vd = -Vd + (Vn * Vm). |
| vhadd | VHADD<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Add elements and shift right by 1 (Average). |
| vhsub | VHSUB<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Subtract elements and shift right by 1. |
| vjcvt | VJCVT<c>.S32.F64 <Sd>, <Dm> | VFP Convert | VFP (JS) | Converts double to signed 32-bit integer (JS semantics). |
| vld1 | VLD1<c>.<size> <list>, [<Rn>]{!} | NEON Load | NEON (SIMD) | Loads vector data from memory (interleaved or sequential). |
| vld2 | VLD2<c>.<size> <list>, [<Rn>]{!} | NEON Load | NEON (SIMD) | De-interleaves 2 streams of data while loading. |
| vld3 | VLD3<c>.<size> <list>, [<Rn>]{!} | NEON Load | NEON (SIMD) | Loads three-element structures (e.g., RGB) and de-interleaves them into three registers. |
| vld4 | VLD4<c>.<size> <list>, [<Rn>]{!} | NEON Load | NEON (SIMD) | Loads four-element structures (e.g., RGBA) and de-interleaves them into four registers. |
| vldm | VLDM<c><mode> <Rn>{!}, <list> | VFP Load Multiple | VFP (Float) | Loads multiple VFP registers from memory. |
| vldr | VLDR<c> <Sd>, [<Rn>, #+/-<imm>] | VFP Load | VFP (Float) | Loads a floating-point register from memory. |
| vmax | VMAX<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Selects maximum value from elements. |
| vmaxnm | VMAXNM<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Returns larger value, handling NaNs per IEEE 754-2008. |
| vmaxnm | VMAXNM<c>.F64 <Dd>, <Dn>, <Dm> | VFP Misc | VFP (Float) | Returns larger double-precision value, handling NaNs. |
| vmin | VMIN<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Selects minimum value from elements. |
| vminnm | VMINNM<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Returns smaller value, handling NaNs per IEEE 754-2008. |
| vminnm | VMINNM<c>.F64 <Dd>, <Dn>, <Dm> | VFP Misc | VFP (Float) | Returns smaller double-precision value, handling NaNs. |
| vmla | VMLA<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Sd = Sd + (Sn * Sm). |
| vmla | VMLA<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Multiplies and adds to accumulator. |
| vmls | VMLS<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Sd = Sd - (Sn * Sm). |
| vmls | VMLS<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Multiplies and subtracts from accumulator. |
| vmmla | VMMLA<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (MatMul) | Matrix multiply-accumulate (BFloat16/Int8). |
| vmov | VMOV<c>.F64 <Dd>, <Dm> | VFP Move | VFP (Float) | Moves data between Double registers. |
| vmov | VMOV<c> <Rt>, <Rt2>, <Dm> | VFP Transfer | VFP (Float) | Moves a Double register to/from two Core registers. |
| vmov | VMOV<c>.F32 <Sd>, <Sm> | VFP Move | VFP (Float) | Moves data between VFP registers. |
| vmov | VMOV<c> <Sn>, <Rt> | VFP Transfer | VFP (Float) | Moves data between Core registers (R) and VFP registers (S). |
| vmov | VMOV<c>.<dt> <Qd>, #<imm> | NEON Imm | NEON (SIMD) | Moves immediate value into vector. |
| vmovl | VMOVL<c>.<dt> <Qd>, <Dm> | NEON 2-Reg | NEON (SIMD) | Copies N-bit elements to 2N-bit elements (Widening). |
| vmovn | VMOVN<c>.<dt> <Dd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Copies 2N-bit elements to N-bit elements (Narrowing). |
| vmrs | VMRS<c> <Rt>, <spec_reg> | VFP System | VFP (System) | Reads a VFP system register (like FPSCR). |
| vmsr | VMSR<c> <spec_reg>, <Rt> | VFP System | VFP (System) | Writes to a VFP system register. |
| vmul | VMUL<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Multiplies two floating-point values. |
| vmul | VMUL<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Multiplies elements. |
| vmull | VMULL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Multiplies N-bit elements producing 2N-bit results. |
| vmvn | VMVN<c> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Moves bitwise inverse of immediate/register. |
| vneg | VNEG<c>.F64 <Dd>, <Dm> | VFP Unary | VFP (Float) | Negates double-precision register. |
| vneg | VNEG<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Negates the value. |
| vneg | VNEG<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Negates integer/float elements. |
| vnmul | VNMUL<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Sd = -(Sn * Sm). |
| vorn | VORN<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Bitwise OR with NOT (Vd = Vn | ~Vm). |
| vorr | VORR<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Bitwise OR of two vectors. |
| vpadal | VPADAL<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Adds adjacent pairs and accumulates into wide destination. |
| vpadd | VPADD<c>.<dt> <Dd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Adds adjacent pairs of elements. |
| vpaddl | VPADDL<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Adds adjacent pairs and produces wide result. |
| vpmax | VPMAX<c>.<dt> <Dd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Maximum of adjacent pairs. |
| vpmin | VPMIN<c>.<dt> <Dd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Minimum of adjacent pairs. |
| vpop | VPOP <list> | VFP Load Multiple | VFP (Float) | Pops VFP registers from the stack (Alias for VLDMIA SP!). |
| vpush | VPUSH <list> | VFP Store Multiple | VFP (Float) | Pushes VFP registers to the stack (Alias for VSTMDB SP!). |
| vqadd | VQADD<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Adds elements with saturation. |
| vqdmlal | VQDMLAL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Multiplies, doubles, saturates, and adds to accumulator (High precision DSP). |
| vqdmlsl | VQDMLSL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Multiplies, doubles, saturates, and subtracts from accumulator. |
| vqdmulh | VQDMULH<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Multiplies, doubles, saturates, and keeps high half. |
| vqdmull | VQDMULL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | NEON (SIMD) | Multiplies narrow elements, doubles, and saturates into wide elements. |
| vqrdmulh | VQRDMULH<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Fixed-point multiply with rounding and saturation. |
| vqrshl | VQRSHL<c>.<dt> <Qd>, <Qm>, <Qn> | NEON 3-Reg | NEON (SIMD) | Shifts left with saturation and rounding. |
| vqrshrn | VQRSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right, saturates, rounds, and narrows. |
| vqshl | VQSHL<c>.<dt> <Qd>, <Qm>, <Qn> | NEON 3-Reg | NEON (SIMD) | Shifts left with saturation based on register. |
| vqshl | VQSHL<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts left with saturation based on immediate. |
| vqshlu | VQSHLU<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts signed elements left, saturating to unsigned result. |
| vqshr | VQSHR<c>.U<size> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right with saturation (Unsigned). |
| vqshrn | VQSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right, saturates, and narrows. |
| vqsub | VQSUB<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Subtracts elements with saturation. |
| vraddhn | VRADDHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Adds wide elements, rounds, and returns high narrow half. |
| vrecpe | VRECPE<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Estimates reciprocal (1/x). |
| vrecps | VRECPS<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Newton-Raphson step for reciprocal refinement: (2 - Vn * Vm). |
| vrev16 | VREV16<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Reverses bytes within 16-bit halfwords. |
| vrev32 | VREV32<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Reverses elements within 32-bit words. |
| vrev64 | VREV64<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Reverses elements within 64-bit doublewords. |
| vrinta | VRINTA<c>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Rounds float to integral float (Nearest). |
| vrintm | VRINTM<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Rounds float towards Minus Infinity (Floor). |
| vrintm | VRINTM<c>.F64 <Dd>, <Dm> | VFP Unary | VFP (Float) | Rounds double towards Minus Infinity (Floor). |
| vrintn | VRINTN<c>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Rounds float to integral float (Nearest Even). |
| vrintp | VRINTP<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Rounds float towards Plus Infinity (Ceil). |
| vrintp | VRINTP<c>.F64 <Dd>, <Dm> | VFP Unary | VFP (Float) | Rounds double towards Plus Infinity (Ceil). |
| vrintr | VRINTR<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Rounds float to integral float using FPSCR rounding mode. |
| vrintx | VRINTX<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Rounds float to integral float, raising Inexact exception. |
| vrintz | VRINTZ<c>.F32 <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Rounds float to integral float (Towards Zero). |
| vrshl | VRSHL<c>.<dt> <Qd>, <Qm>, <Qn> | NEON 3-Reg | NEON (SIMD) | Shifts left with rounding based on a register value. |
| vrshr | VRSHR<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right with rounding based on immediate. |
| vrshrn | VRSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right, rounds, and narrows (2N -> N bits). |
| vrsqrte | VRSQRTE<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Estimates reciprocal square root (1/sqrt(x)). |
| vrsqrts | VRSQRTS<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2. |
| vrsra | VRSRA<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right with rounding and adds to accumulator. |
| vrsubhn | VRSUBHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Subtracts wide elements, rounds, and returns high narrow half. |
| vsel | VSEL<cond>.F32 <Sd>, <Sn>, <Sm> | VFP Misc | VFP (Float) | Selects elements from Dn or Dm based on condition flags (predicated VFP). |
| vsel | VSEL<cond>.F64 <Dd>, <Dn>, <Dm> | VFP Misc | VFP (Float) | Selects between two double-precision registers based on flags. |
| vshl | VSHL<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts elements left. |
| vshr | VSHR<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts elements right. |
| vshrn | VSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts right and narrows result. |
| vsli | VSLI<c>.<size> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts bits left and inserts into destination (merging). |
| vsmmla | VSMMLA<c>.S8 <Qd>, <Qn>, <Qm> | NEON MatMul | NEON (MatMul) | Matrix multiply-accumulate (Signed Int8). |
| vsqrt | VSQRT<c>.F64 <Dd>, <Dm> | VFP Unary | VFP (Float) | Square root of double-precision register. |
| vsqrt | VSQRT<c>.F32 <Sd>, <Sm> | VFP Unary | VFP (Float) | Calculates square root. |
| vsra | VSRA<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts elements right and adds to the destination accumulator. |
| vsri | VSRI<c>.<size> <Qd>, <Qm>, #<imm> | NEON Shift | NEON (SIMD) | Shifts bits right and inserts into destination. |
| vst1 | VST1<c>.<size> <list>, [<Rn>]{!} | NEON Store | NEON (SIMD) | Stores vector data to memory. |
| vst3 | VST3<c>.<size> <list>, [<Rn>]{!} | NEON Store | NEON (SIMD) | Interleaves and stores three registers into memory (e.g., RGB). |
| vst4 | VST4<c>.<size> <list>, [<Rn>]{!} | NEON Store | NEON (SIMD) | Interleaves and stores four registers into memory (e.g., RGBA). |
| vstm | VSTM<c><mode> <Rn>{!}, <list> | VFP Store Multiple | VFP (Float) | Stores multiple VFP registers to memory. |
| vstr | VSTR<c> <Sd>, [<Rn>, #+/-<imm>] | VFP Store | VFP (Float) | Stores a floating-point register to memory. |
| vsub | VSUB<c>.F32 <Sd>, <Sn>, <Sm> | VFP Arith | VFP (Float) | Subtracts two floating-point values. |
| vsub | VSUB<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Subtracts integer elements. |
| vsubhn | VSUBHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Subtracts wide elements and returns high narrow half. |
| vswp | VSWP<c> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Swaps the contents of two vectors. |
| vtbl | VTBL<c>.8 <Dd>, <list>, <Dm> | NEON Table | NEON (SIMD) | Look up elements in a vector table. |
| vtbx | VTBX<c>.8 <Dd>, <list>, <Dm> | NEON Table | NEON (SIMD) | Inserts elements into a vector using a table lookup. |
| vtrn | VTRN<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Transposes elements of two vectors. |
| vtst | VTST<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | NEON (SIMD) | Tests if any bits match (Vd = (Vn & Vm) != 0). |
| vummla | VUMMLA<c>.U8 <Qd>, <Qn>, <Qm> | NEON MatMul | NEON (MatMul) | Matrix multiply-accumulate (Unsigned Int8). |
| vusdot | VUSDOT<c>.S8 <Qd>, <Qn>, <Qm> | NEON DotProd | NEON (DotProd) | Dot product of unsigned (src1) and signed (src2) bytes. |
| vusmmla | VUSMMLA<c>.S8 <Qd>, <Qn>, <Qm> | NEON MatMul | NEON (MatMul) | Matrix multiply-accumulate (Unsigned x Signed Int8). |
| vuzp | VUZP<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | De-interleaves vectors. |
| vzip | VZIP<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | NEON (SIMD) | Interleaves vectors. |
| wfe | WFE | System Alias | Base | Puts the processor into a low-power state until an event occurs. |
| wfe | WFE | System Hint | A32 (Base) | Enters low-power state until an event occurs. |
| wfe | WFE | Thumb System | A32 (Base) | Wait for event (Thumb). |
| wfet | WFET <Wn> | System | Base (v8.7) | Waits for an event or a timeout (using a counter). |
| wfi | WFI | System Alias | Base | Puts the processor into a low-power state until an interrupt occurs. |
| wfi | WFI | System Hint | A32 (Base) | Enters low-power state until an interrupt occurs. |
| wfi | WFI | Thumb System | A32 (Base) | Wait for interrupt (Thumb). |
| wfit | WFIT <Wn> | System | Base (v8.7) | Waits for an interrupt or a timeout. |
| whilehi | WHILEHI <Pd>.<T>, <Xn>, <Xm> | SVE Compare | SVE | Generates predicate for unsigned loop (while Xn > Xm). |
| whilehs | WHILEHS <Pd>.<T>, <Xn>, <Xm> | SVE Compare | SVE | Generates predicate for unsigned loop (while Xn >= Xm). |
| whilele | WHILELE <Pd>.<T>, <Xn>, <Xm> | SVE Compare Scalar | SVE | Generates a predicate based on loop counter (while Xn <= Xm). |
| whilelo | WHILELO <Pd>.<T>, <Xn>, <Xm> | SVE Compare | SVE | Generates predicate for unsigned loop (while Xn < Xm). |
| whilels | WHILELS <Pd>.<T>, <Xn>, <Xm> | SVE Compare | SVE | Generates predicate for unsigned loop (while Xn <= Xm). |
| whilelt | WHILELT <Pd>.<T>, <Xn>, <Xm> | SVE Compare Scalar | SVE | Generates a predicate based on a loop counter (while Xn < Xm). |
| xpacd | XPACD <Xd> | Data Processing | PAC (Security) | Removes the PAC signature from a data pointer. |
| xpaci | XPACI <Xd> | Data Processing | PAC (Security) | Removes the PAC signature from an instruction pointer. |
| xpaclri | XPACLRI | System | PAC (Security) | Removes the pointer authentication code from an instruction address. |
| xtn | XTN <Vd>.<Tb>, <Vn>.<Ta> | SIMD Shift Imm | NEON (SIMD) | Reads elements, narrows them, and writes to lower half of destination. |
| yield | YIELD | System Alias | Base | Hints that the current thread is performing a spin-wait loop. |
| yield | YIELD | System Hint | A32 (Base) | Hints that the task is performing a spin-wait. |
| yield | YIELD | Thumb System | A32 (Base) | Yield hint (Thumb). |
| zip1 | ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | Interleaves the lower halves of two vectors. |
| zip1 | ZIP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Interleaves elements from the lower halves. |
| zip2 | ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | NEON (SIMD) | Interleaves the upper halves of two vectors. |
| zip2 | ZIP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | SVE Permute | SVE | Interleaves elements from the upper halves. |