ARM Instructions
1145 instructions - showing 100 per page, page 1 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| abs | ABS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Integer Unary | SVE | Calculates absolute value of integers. |
| abs | ABS <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Calculates absolute value of integer elements. |
| adc | ADC <Wd>, <Wn>, <Wm> | Data Processing (3-source) | Base | Adds two register values and the Carry flag. |
| adc | ADC <Xd>, <Xn>, <Xm> | Data Processing (3-source) | Base | Adds two 64-bit register values and the Carry flag. |
| adc | ADC{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Adds two 32-bit values and the Carry flag. |
| adc.w | ADC.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit add with carry (Access high registers/large constants). |
| adcs | ADCS <Wd>, <Wn>, <Wm> | Data Processing (3-source) | Base | Adds two register values and Carry, updating NZCV flags. |
| adcs | ADCS <Xd>, <Xn>, <Xm> | Data Processing (3-source) | Base | Adds two 64-bit register values and Carry, updating NZCV flags. |
| add | ADD <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing (Register) | Base | Adds a register value and a sign/zero-extended register value. |
| add | ADD <Xd|SP>, <Xn|SP>, <R><m> {, <extend> {#<amount>}} | Data Processing (Register) | Base | Adds a 64-bit register and an extended register value. |
| add | ADD <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Base | Adds a register value and an immediate value. |
| add | ADD <Xd|SP>, <Xn|SP>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Base | Adds a 64-bit register value and an immediate value. |
| add | ADD <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing (Register) | Base | Adds a register value and a shifted register value. |
| add | ADD <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Data Processing (Register) | Base | Adds a 64-bit register value and a shifted register value. |
| add | ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds corresponding elements in two vectors. |
| add | ADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE | Adds two vectors under predicate control. |
| add | ADD{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Adds two 32-bit values. |
| add.w | ADD.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit add. |
| addg | ADDG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> | Data Processing | MTE (Memory Tagging) | Adds an immediate to an address, modifying the Allocation Tag (MTE). |
| addp | ADDP <Dd>, <Vn>.<T> | NEON Scalar | NEON (Scalar) | Adds two 64-bit values to a 64-bit result (Scalar NEON). |
| addp | ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds adjacent pairs of elements. |
| adds | ADDS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing (Register) | Base | Adds and updates flags (Extended Register). |
| adds | ADDS <Xd>, <Xn|SP>, <R><m> {, <extend> {#<amount>}} | Data Processing (Register) | Base | Adds and updates flags (Extended Register 64-bit). |
| adds | ADDS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Base | Adds immediate and updates flags. |
| adds | ADDS <Xd>, <Xn|SP>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Base | Adds immediate and updates flags (64-bit). |
| adds | ADDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing (Register) | Base | Adds shifted register and updates flags. |
| adds | ADDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Data Processing (Register) | Base | Adds shifted register and updates flags (64-bit). |
| addv | ADDV <V><d>, <Vn>.<T> | SIMD Across Lane | NEON (SIMD) | Adds all elements of the vector into a scalar result. |
| adr | ADR <Xd>, <label> | PC-rel | Base | Calculates the address of a label (PC +/- 1MB range). |
| adr | ADR <Rd>, <label> | Thumb Data Proc | T32 (Thumb) | Adds an immediate value to the PC (Thumb). |
| adr | ADR<c> <Rd>, <label> | Data Proc | A32 (Base) | Adds an immediate value to the PC register. |
| adr.w | ADR.W <Rd>, <label> | Thumb Data Proc | T32 (Thumb2) | Thumb-2 32-bit ADR. |
| adrp | ADRP <Xd>, <label> | PC-rel | Base | Calculates page address of a label (PC +/- 4GB range). |
| aesd | AESD.8 <Qd>, <Qm> | Crypto 2-Reg | Crypto | Performs one round of AES decryption (AArch32). |
| aesd | AESD <Vd>.16B, <Vm>.16B | Crypto | Crypto | AES single round decryption (AArch64 NEON). |
| aesd | AESD <Vd>.<T>, <Vn>.<T> | Crypto | Crypto | Performs one round of AES decryption. |
| aese | AESE.8 <Qd>, <Qm> | Crypto 2-Reg | Crypto | Performs one round of AES encryption (AArch32). |
| aese | AESE <Vd>.16B, <Vm>.16B | Crypto | Crypto | AES single round encryption (AArch64 NEON). |
| aese | AESE <Vd>.<T>, <Vn>.<T> | Crypto | Crypto | Performs one round of AES encryption. |
| aesimc | AESIMC.8 <Qd>, <Qm> | Crypto 2-Reg | Crypto | AES Inverse Mix Columns transformation. |
| aesimc | AESIMC <Vd>.<T>, <Vn>.<T> | Crypto | Crypto | Performs AES Inverse Mix Columns transformation. |
| aesmc | AESMC.8 <Qd>, <Qm> | Crypto 2-Reg | Crypto | AES Mix Columns transformation. |
| aesmc | AESMC <Vd>.<T>, <Vn>.<T> | Crypto | Crypto | Performs AES Mix Columns transformation. |
| and | AND <Wd|Wsp>, <Wn>, #<imm> | Logical (Immediate) | Base | Bitwise AND with logical immediate. |
| and | AND <Xd|SP>, <Xn>, #<imm> | Logical (Immediate) | Base | Bitwise AND with logical immediate (64-bit). |
| and | AND <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | Bitwise AND with shifted register. |
| and | AND <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Base | Bitwise AND with shifted register (64-bit). |
| and | AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Bitwise AND of two vectors. |
| and | AND <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE | Bitwise AND of two vectors under predicate. |
| and | AND{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Performs a bitwise AND on two 32-bit values. |
| and.w | AND.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit AND. |
| ands | ANDS <Wd>, <Wn>, #<imm> | Logical (Immediate) | Base | Bitwise AND immediate, updates flags. |
| ands | ANDS <Xd>, <Xn>, #<imm> | Logical (Immediate) | Base | Bitwise AND immediate, updates flags (64-bit). |
| ands | ANDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | Bitwise AND shifted register, updates flags. |
| ands | ANDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Base | Bitwise AND shifted register, updates flags (64-bit). |
| andv | ANDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | ANDs all active elements into a scalar. |
| asr | ASR <Wd>, <Wn>, #<shift> | Data Processing (Immediate) | Base | Arithmetic shift right by immediate. |
| asr | ASR <Xd>, <Xn>, #<shift> | Data Processing (Immediate) | Base | Arithmetic shift right by immediate (64-bit). |
| asr | ASR <Wd>, <Wn>, <Wm> | Data Processing (Register) | Base | Arithmetic shift right by register value. |
| asr | ASR <Xd>, <Xn>, <Xm> | Data Processing (Register) | Base | Arithmetic shift right by register value (64-bit). |
| asr | ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Shift | SVE | Shifts elements right arithmetically under predicate. |
| asr | ASR{S}<c> <Rd>, <Rm>, <Rs> | Data Proc | A32 (Base) | Arithmetic right shift (sign-extending). |
| at | AT S1E1R, <Xt> | System | Base (System) | Performs stage 1 address translation for current EL. |
| at | AT S1E1W, <Xt> | System | Base (System) | Performs stage 1 address translation for write permission. |
| at | AT <op>, <Xt> | System Alias | System | Translates a virtual address to a physical address (for debug/software). |
| autda | AUTDA <Xd>, <Xn> | Data Processing | PAC (Security) | Authenticates a data address signed with Key A. |
| autdb | AUTDB <Xd>, <Xn> | Data Processing | PAC (Security) | Authenticates a data address signed with Key B. |
| autia | AUTIA <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Authenticates a pointer signed with Key A. Corrupts pointer if failed. |
| autia | AUTIA <Xd>, <Xn> | Data Processing | PAC (Security) | Authenticates an instruction address signed with Key A. |
| autib | AUTIB <Xd>, <Xn|SP> | Data Processing | PAC (Security) | Authenticates a pointer signed with Key B. |
| autib | AUTIB <Xd>, <Xn> | Data Processing | PAC (Security) | Authenticates an instruction address signed with Key B. |
| b | B <label> | Branch | Base | Unconditional branch to label. |
| b | B<c> <label> | Branch | A32 (Base) | Branch relative (PC +/- 32MB). |
| b.cond | B.cond <label> | Branch | Base | Branch if condition is met (e.g., B.EQ, B.NE). |
| b.w | B.W <label> | Thumb Branch | T32 (Thumb2) | Thumb-2 32-bit Unconditional Branch (large range). |
| bc.cond | BC.cond <label> | Branch | Base (v8.8) | Branch if condition is met, with stronger ordering guarantees. |
| bfadd | BFADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | FEAT_SVE_B16B16 | Adds BFloat16 elements. |
| bfc | BFC <Rd>, #<lsb>, #<width> | Thumb Bitfield | A32 (Base) | Clears a bitfield in a register. |
| bfc | BFC<c> <Rd>, #<lsb>, #<width> | Data Proc | A32 (Base) | Clears a bitfield in a register. |
| bfcvtn | BFCVTN <Vd>.<Tb>, <Vn>.<Ta> | NEON 2-Reg | FEAT_BF16 (AI) | Converts Float32 to BFloat16 (Lower Half). |
| bfcvtn2 | BFCVTN2 <Vd>.<Tb>, <Vn>.<Ta> | NEON 2-Reg | FEAT_BF16 (AI) | Converts Float32 to BFloat16 (Upper Half). |
| bfdot | BFDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_BF16 (AI) | Computes dot product of BFloat16 elements, accumulating to Float32 (NEON). |
| bfi | BFI <Rd>, <Rn>, #<lsb>, #<width> | Thumb Bitfield | A32 (Base) | Inserts a bitfield into a register. |
| bfi | BFI<c> <Rd>, <Rn>, #<lsb>, #<width> | Data Proc | A32 (Base) | Copies a bitfield into a register. |
| bfm | BFM <Wd>, <Wn>, #<immr>, #<imms> | Bitfield | Base | Moves a bitfield from source to destination. |
| bfm | BFM <Xd>, <Xn>, #<immr>, #<imms> | Bitfield | Base | Moves a bitfield from source to destination (64-bit). |
| bfmax | BFMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | FEAT_SVE_B16B16 | Calculates maximum of BFloat16 elements. |
| bfmin | BFMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | FEAT_SVE_B16B16 | Calculates minimum of BFloat16 elements. |
| bfmmla | BFMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | FEAT_BF16 (AI) | Performs 2x2 matrix multiplication on BFloat16 tiles (NEON). |
| bfmul | BFMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | FEAT_SVE_B16B16 | Multiplies BFloat16 elements. |
| bfsub | BFSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | FEAT_SVE_B16B16 | Subtracts BFloat16 elements. |
| bic | BIC <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | ANDs register with NOT of shifted register (AND NOT). |
| bic | BIC <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Base | ANDs register with NOT of shifted register (64-bit). |
| bic | BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | ANDs Vd with NOT of Vm. |
| bic | BIC <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE | Bitwise AND NOT of two vectors under predicate. |
| bic | BIC{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Performs AND NOT (Rd = Rn & ~Rm). |
| bic.w | BIC.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit AND NOT. |
| bics | BICS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | Performs BIC and updates flags. |
| bics | BICS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Base | Performs BIC and updates flags (64-bit). |
| bif | BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Inserts bits from Vn into Vd where Vm (mask) is 0. |