uxth

Unsigned Extend Halfword (A32)

UXTH<c> <Rd>, <Rm> {, <rotation>}

Zero-extends the low halfword to 32-bits.

Details

Zero-extends the low halfword (bits [15:0]) of Rm to the full 32-bit width and stores the result in Rd. An optional rotation (0°, 90°, 180°, or 270°) can be applied to Rm before the extension. No condition flags are affected by this instruction. A32 only; executes in User and Privileged modes.

Pseudocode Operation

rotated ← ROR(Rm, rotation * 8)
Rd ← ZeroExtend(rotated[15:0], 32)

Example

UXTH r0, r2

Encoding

Binary Layout
cond
01101
1
11
1111
Rd
rotate
0
0
0111
Rm
 
Format Data Proc
Opcode 0x06FF0070
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06FF0070 UXTH{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>} A32 cond | 01101 | 1 | 11 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm
0xB280 UXTH{<c>}{<q>} {<Rd>,} <Rm> T32 10110010 | 1 | 0 | Rm | Rd
0xFA1FF080 UXTH{<c>}.W {<Rd>,} <Rm> T32 111110100 | 00 | 1 | 1111 | 1111 | Rd | 1 | 0 | rotate | Rm

Description

Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d] = ZeroExtend(rotated<15:0>, 32);