aesmc

AES Mix Columns

AESMC <Vd>.<T>, <Vn>.<T>

Performs AES Mix Columns transformation.

Pseudocode Operation

Vd ← AES_MixColumns(Vn)

Example

AESMC v0.4s.T, v1.4s.T

Encoding

Binary Layout

01001110

31:24

00

23:22

101000011

21:13

0

12

10

11:10

Rn

9:5

Rd

4:0

 

Format Crypto

Opcode 0x4E286800

Extension Crypto

Operands

• Vd
  Destination SIMD/FP vector register
• Vn
  First source SIMD/FP vector register

Related

Other forms of aesmc

• aesmc AES Mix Columns (A32)

More in Crypto

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x4E286800	AESMC <Vd>.16B, <Vn>.16B		A64		01001110 | 00 | 101000011 | 0 | 10 | Rn | Rd
0x4520E000	AESMC <Zdn>.B, <Zdn>.B		A64		01000101 | 0 | 0 | 10000011100 | 0 | 00000 | Zdn

Description

AES mix columns.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) operand = V[n, 128];
bits(128) result;
result = AESMixColumns(operand);
V[d, 128] = result;