aesmc

AES Mix Columns

AESMC <Vd>.<T>, <Vn>.<T>

Performs AES Mix Columns transformation.

Details

Performs the AES Mix Columns transformation on a 128-bit vector. The instruction applies the MixColumns operation to the bytes in Vn and stores the result in Vd. This is an AArch64-only instruction requiring the Crypto extension. No condition flags are affected.

Pseudocode Operation

Vd ← AES_MixColumns(Vn)

Example

AESMC v0.4s.T, v1.4s.T

Encoding

Binary Layout
01001110
00
101000011
0
10
Rn
Rd
 
Format Crypto
Opcode 0x4E286800
Extension Crypto

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x4E286800 AESMC <Vd>.16B, <Vn>.16B A64 01001110 | 00 | 101000011 | 0 | 10 | Rn | Rd
0x4520E000 AESMC <Zdn>.B, <Zdn>.B A64 01000101 | 0 | 0 | 10000011100 | 0 | 00000 | Zdn

Description

AES mix columns.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) operand = V[n, 128];
bits(128) result;
result = AESMixColumns(operand);
V[d, 128] = result;