bics

Bitwise Bit Clear and Set Flags

BICS <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Performs BIC and updates flags.

Pseudocode Operation

operand2 ← Wm
if shift != NONE then
  operand2 ← operand2 shift_op amount
result ← Wn & ~operand2
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← 0
V ← 0

Example

BICS w0, w1, w2

Encoding

Binary Layout

0

31

11

30:29

01010

28:24

shift

23:22

1

21

Rm

20:16

imm6

15:10

Rn

9:5

Rd

4:0

 

Format Logical (Register)

Opcode 0x6A200000

Extension Base

Operands

• Wd
  Destination 32-bit integer register
• Wn
  First source / base 32-bit integer register
• Wm
  Second source / offset 32-bit integer register

Related

Other forms of bics

• bics Bitwise Bit Clear and Set Flags (64-bit)

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x6A200000	BICS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}		A64		0 | 11 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0xEA200000	BICS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}		A64		1 | 11 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0x25404010	BICS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B		A64		00100101 | 0 | 1 | 00 | Pm | 01 | Pg | 0 | Pn | 1 | Pd

Description

Bitwise Bit Clear (shifted register), setting flags, performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.

Operation

bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
bits(datasize) result;

operand2 = NOT(operand2);

result = operand1 AND operand2;
PSTATE.<N,Z,C,V> = result<datasize-1>:IsZeroBit(result):'00';

X[d, datasize] = result;