prfm

Prefetch Memory (Literal)

PRFM <prfop>, <label>

Prefetches data from a PC-relative address.

Pseudocode Operation

address ← PC + (imm19 << 2); Prefetch(address, prfop);

Example

PRFM prfop, label

Encoding

Binary Layout

31:30

011

29:27

25:24

imm19

23:5

4:0

Format Load Literal

Opcode 0xD8000000

Extension Base

Operands

prfop
Type
label
Label

Other forms of prfm

prfm Prefetch Memory (Immediate)
prfm Prefetch Memory (Register)

Across architectures

Cache Prefetch Hint : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0xF9800000	PRFM (<prfop>\|#<imm5>), [<Xn\|SP>{, #<pimm>}]	A64	11 \| 111 \| 0 \| 01 \| 10 \| imm12 \| Rn \| Rt
0xD8000000	PRFM (<prfop>\|#<imm5>), <label>	A64	11 \| 011 \| 0 \| 00 \| imm19 \| Rt
0xF8A04800	PRFM (<prfop>\|#<imm5>), [<Xn\|SP>, (<Wm>\|<Xm>){, <extend> {<amount>}}]	A64	11 \| 111 \| 0 \| 00 \| 10 \| 1 \| Rm \| option \| S \| 10 \| Rn \| Rt

Description

Prefetch Memory (literal) signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into one or more caches. The effect of a PRFM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address = PC64 + offset;

Prefetch(address, t<4:0>);