bic.w

Bitwise Bit Clear (Wide)

BIC.W <Rd>, <Rn>, <Operand2>

Thumb-2 32-bit AND NOT.

Details

Performs a bitwise AND of Rn with the bitwise NOT of the shifted Operand2, effectively clearing bits in Rn where Operand2 has set bits. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.

Pseudocode Operation

result ← Rn AND NOT Operand2
Rd ← result
if S == 1 then
  CPSR.N ← result[31]
  CPSR.Z ← (result == 0)
  CPSR.C ← CarryOut(Operand2)
else
  CPSR.C ← CPSR.C

Example

BIC.W r0, r1, r2

Encoding

Binary Layout
1110101
0001
0
Rn
0
imm3
Rd
imm2
stype
Rm
 
Format Thumb2 Data Proc
Opcode 0xEA200000
Extension T32 (Thumb2)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Operand2
    Flexible second operand (register or shifted register)

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x03C00000 BIC{<c>}{<q>} {<Rd>,} <Rn>, #<const> A32 cond | 00111 | 10 | 0 | Rn | Rd | imm12
0xF0200000 BIC{<c>}{<q>} {<Rd>,} <Rn>, #<const> T32 11110 | i | 0 | 0001 | 0 | Rn | 0 | imm3 | Rd | imm8
0x01C00060 BIC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX A32 cond | 00011 | 10 | 0 | Rn | Rd | 00000 | 11 | 0 | Rm
0x01C00000 BIC{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} A32 cond | 00011 | 10 | 0 | Rn | Rd | imm5 | stype | 0 | Rm
0x4380 BIC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> T32 010000 | 1110 | Rm | Rdn
0xEA200030 BIC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX T32 1110101 | 0001 | 0 | Rn | 0 | 000 | Rd | 00 | 11 | Rm
0xEA200000 BIC<c>.W {<Rd>,} <Rn>, <Rm> T32 1110101 | 0001 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm
0x01C00010 BIC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> A32 cond | 00011 | 10 | 0 | Rn | Rd | Rs | 0 | stype | 1 | Rm

Description

Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. If the destination register is not the PC, the BICS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    result = R[n] AND NOT(shifted);
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.N = result<31>;
            PSTATE.Z = IsZeroBit(result);
            PSTATE.C = carry;
            // PSTATE.V unchanged