stxr

Store Exclusive Register

STXR <Ws>, <Wt>, [<Xn|SP>]

Stores a word if exclusive monitor matches.

Details

Conditionally stores a 32-bit word from Wt to memory at address Xn if the exclusive monitor for that address is marked exclusive; writes the store status (0=success, 1=failure) to Ws. No condition flags are affected. AArch64-only instruction that interacts with the exclusive monitor and may generate exception faults.

Pseudocode Operation

address ← Xn
if ExclusiveMonitorMatch(address, WORD) then
  [address, 4] ← Wt[31:0]
  Ws ← 0
  ClearExclusiveMonitor(address)
else
  Ws ← 1

Example

STXR w6, w3, [x1]

Encoding

Binary Layout
10
0010000
0
0
Rs
0
11111
Rn
Rt
 
Format Load/Store Excl
Opcode 0x88007C00
Extension Base (Atomic)

Operands

  • Ws
    Status
  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x88007C00 STXR <Ws>, <Wt>, [<Xn|SP>{, #0}] A64 10 | 0010000 | 0 | 0 | Rs | 0 | 11111 | Rn | Rt
0xC8007C00 STXR <Ws>, <Xt>, [<Xn|SP>{, #0}] A64 11 | 0010000 | 0 | 0 | Rs | 0 | 11111 | Rn | Rt

Description

Store Exclusive Register stores a 32-bit word or a 64-bit doubleword from a register to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(elsize) data;
constant integer dbytes = elsize DIV 8;

AccessDescriptor accdesc = CreateAccDescExLDST(MemOp_STORE, FALSE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
elsif rn_unknown then
    address = bits(64) UNKNOWN;
else
    address = X[n, 64];

if rt_unknown then
    data = bits(elsize) UNKNOWN;
else
    data = X[t, elsize];

bit status = '1';
// Check whether the Exclusives monitors are set to include the
// physical memory locations corresponding to virtual address
// range [address, address+dbytes-1].

// If AArch64.ExclusiveMonitorsPass() returns FALSE and the memory address,
// if accessed, would generate a synchronous Data Abort exception, it is
// IMPLEMENTATION DEFINED whether the exception is generated.
// It is a limitation of this model that synchronous Data Aborts are never
// generated in this case, as Mem[] is not called.
// If FEAT_SPE is implemented, it is also IMPLEMENTATION DEFINED whether or not the
// physical address packet is output when permitted and when
// AArch64.ExclusiveMonitorPass() returns FALSE for a Store Exclusive instruction.
// This behavior is not reflected here due to the previously stated limitation.
if AArch64.ExclusiveMonitorsPass(address, dbytes, accdesc) then
    // This atomic write will be rejected if it does not refer
    // to the same physical locations after address translation.
    Mem[address, dbytes, accdesc] = data;
    status = ExclusiveMonitorsStatus();
X[s, 32] = ZeroExtend(status, 32);