asr

Arithmetic Shift Right (Register)

ASR <Wd>, <Wn>, <Wm>

Arithmetic shift right by register value.

Details

Performs an arithmetic right shift of Wn by the value in Wm (modulo 32), storing the result in Wd. The sign bit (bit 31) is replicated into vacated bit positions. No condition flags are affected.

Pseudocode Operation

Wd ← Wn >> (Wm AND 0x1F) (arithmetic, sign-extended)

Example

ASR w0, w1, w2

Encoding

Binary Layout
0
0
0
11010110
Rm
0010
10
Rn
Rd
 
Format Data Processing (Register)
Opcode 0x1AC02800
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • Wm
    Shift Reg

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1AC02800 ASR <Wd>, <Wn>, <Wm> A64 0 | 0 | 0 | 11010110 | Rm | 0010 | 10 | Rn | Rd
0x9AC02800 ASR <Xd>, <Xn>, <Xm> A64 1 | 0 | 0 | 11010110 | Rm | 0010 | 10 | Rn | Rd
0x13007C00 ASR <Wd>, <Wn>, #<shift> A64 0 | 00 | 100110 | 0 | immr | 011111 | Rn | Rd
0x9340FC00 ASR <Xd>, <Xn>, #<shift> A64 1 | 00 | 100110 | 1 | immr | 111111 | Rn | Rd
0x04008000 ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> A64 00000100 | tszh | 00 | 0 | 0 | 0 | 0 | 100 | Pg | tszl | imm3 | Zdn
0x04188000 ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D A64 00000100 | size | 011 | 0 | 0 | 0 | 100 | Pg | Zm | Zdn
0x04108000 ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 010 | 0 | 0 | 0 | 100 | Pg | Zm | Zdn
0x04209000 ASR <Zd>.<T>, <Zn>.<T>, #<const> A64 00000100 | tszh | 1 | tszl | imm3 | 1001 | 0 | 0 | Zn | Zd
0x04208000 ASR <Zd>.<T>, <Zn>.<T>, <Zm>.D A64 00000100 | size | 1 | Zm | 1000 | 0 | 0 | Zn | Zd

Description

Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The remainder obtained by dividing the second source register by the data size defines the number of bits by which the first source register is right-shifted.