vhadd

Vector Halving Add

VHADD<c>.<dt> <Qd>, <Qn>, <Qm>

Add elements and shift right by 1 (Average).

Details

The Vector Halving Add instruction add elements and shift right by 1 (Average).

Pseudocode Operation

Qd ← Qn + Qm
// Flags affected: N, Z, C, V

Example

VHADD.dt q0, q1, q2

Encoding

Binary Layout
11110010
0
sz
0
Vn
Vd
0000
N
Q
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2000000
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register