vusdot

Vector Unsigned-Signed Dot Product (A32)

VUSDOT<c>.S8 <Qd>, <Qn>, <Qm>

Dot product of unsigned (src1) and signed (src2) bytes.

Details

Computes the dot product of unsigned 8-bit integers from Qn and signed 8-bit integers from Qm, accumulating four dot products (one per 32-bit lane) into the corresponding 32-bit signed integer elements of Qd. Each lane multiplies and sums four pairs of unsigned×signed bytes. Condition flags are unaffected. This instruction requires the NEON DotProd extension and executes in A32 (ARM) instruction set only.

Pseudocode Operation

for i = 0 to 3 do
  acc = Qd[i*32 + 0:31]
  for j = 0 to 3 do
    unsigned_byte = ZeroExtend(Qn[(i*4 + j)*8 + 0:7])
    signed_byte = SignExtend(Qm[(i*4 + j)*8 + 0:7])
    acc = acc + (unsigned_byte * signed_byte)
  Qd[i*32 + 0:31] = acc

Example

VUSDOT.S8 q0, q1, q2

Encoding

Binary Layout
1111110
01
D
10
Vn
Vd
1
1
0
1
N
1
M
0
Vm
 
Format NEON DotProd
Opcode 0xFCA00D40
Extension NEON (DotProd)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    Unsigned
  • Qm
    Signed

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xFCA00D00 VUSDOT{<q>}.S8 <Dd>, <Dn>, <Dm> A32 1111110 | 01 | D | 10 | Vn | Vd | 1 | 1 | 0 | 1 | N | 0 | M | 0 | Vm
0xFCA00D40 VUSDOT{<q>}.S8 <Qd>, <Qn>, <Qm> A32 1111110 | 01 | D | 10 | Vn | Vd | 1 | 1 | 0 | 1 | N | 1 | M | 0 | Vm
0xFE800D00 VUSDOT{<q>}.S8 <Dd>, <Dn>, <Dm>[<index>] A32 11111110 | 1 | D | 00 | Vn | Vd | 110 | 1 | N | 0 | M | 0 | Vm
0xFE800D40 VUSDOT{<q>}.S8 <Qd>, <Qn>, <Dm>[<index>] A32 11111110 | 1 | D | 00 | Vn | Vd | 110 | 1 | N | 1 | M | 0 | Vm

Description

Dot Product vector form with mixed-sign integers. This instruction performs the dot product of the four unsigned 8-bit integer values in each 32-bit element of the first source register with the four signed 8-bit integer values in the corresponding 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination register. From Armv8.2, this is an optional instruction. ID_ISAR6.I8MM indicates whether this instruction is supported in the T32 and A32 instruction sets.

Operation

CheckAdvSIMDEnabled();
bits(64) operand1;
bits(64) operand2;
bits(64) result;

for r = 0 to regs-1
    operand1 = Din[n+r];
    operand2 = Din[m+r];
    result = Din[d+r];
    for e = 0 to 1
        bits(32) res = Elem[result, e, 32];
        for b = 0 to 3
            element1 = UInt(Elem[operand1, 4 * e + b, 8]);
            element2 = SInt(Elem[operand2, 4 * e + b, 8]);
            res = res + element1 * element2;
        Elem[result, e, 32] = res;
    D[d+r] = result;