sha512h

SHA512 Hash Part 1 (A32)

SHA512H.64 <Qd>, <Qn>, <Qm>

SHA512 hash update part 1.

Details

Performs the first part of the SHA-512 hash computation, processing hash values and round constants. The operation combines Qn (hash) and Qm (data) values and updates Qd (state) with intermediate results. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.

Pseudocode Operation

Qd ← SHA512_H_Part1(Qd, Qn, Qm)

Example

SHA512H.64 q0, q1, q2

Encoding

Binary Layout
11001110011
Rm
1
0
00
00
Rn
Rd
 
Format Crypto 3-Reg
Opcode 0xCE608000
Extension Crypto (SHA512)

Operands

  • Qd
    State
  • Qn
    Hash
  • Qm
    Data

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xCE608000 SHA512H <Qd>, <Qn>, <Vm>.2D A64 11001110011 | Rm | 1 | 0 | 00 | 00 | Rn | Rd

Description

SHA512 Hash update part 1 takes the values from the three 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the sigma1 and chi functions of two iterations of the SHA512 computation. It returns this value to the destination SIMD&FP register. This instruction is implemented only when FEAT_SHA512 is implemented.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vtmp;
bits(64) MSigma1;
bits(64) tmp;
bits(128) x = V[n, 128];
bits(128) y = V[m, 128];
bits(128) w = V[d, 128];

MSigma1 = ROR(y<127:64>, 14) EOR ROR(y<127:64>, 18) EOR ROR(y<127:64>, 41);
Vtmp<127:64> = (y<127:64> AND x<63:0>) EOR (NOT(y<127:64>) AND x<127:64>);
Vtmp<127:64> = (Vtmp<127:64> + MSigma1 + w<127:64>);
tmp = Vtmp<127:64> + y<63:0>;
MSigma1 = ROR(tmp, 14) EOR ROR(tmp, 18) EOR ROR(tmp, 41);
Vtmp<63:0> = (tmp AND y<127:64>) EOR (NOT(tmp) AND x<63:0>);
Vtmp<63:0> = (Vtmp<63:0> + MSigma1 + w<63:0>);
V[d, 128] = Vtmp;