fcvtau

Floating-Point Convert to Unsigned Integer (Nearest)

FCVTAU <Wd|Xd>, <Hn|Sn|Dn>

Converts float to unsigned integer, rounding to nearest.

Details

Converts a scalar floating-point value to an unsigned integer, rounding to nearest with ties away from zero. Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.

Pseudocode Operation

operand ← Vn
intval ← RoundTowardNearestAwayFromZero(operand)
if intval > MaxUInt(destination_width) or intval < 0 then
  GenerateException(InvalidOperation)
else
  Rd ← ZeroExtend(intval)
  UpdateFlags(intval)
end

Example

FCVTAU Wd, Dn

Encoding

Binary Layout
0
0
0
11110
11
1
00
101
000000
Rn
Rd
 
Format FP Conversion
Opcode 0x1EE50000
Extension Floating Point

Operands

  • Rd
    Int Dest
  • Vn
    Float Src

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7E79C800 FCVTAU <Hd>, <Hn> A64 01 | 1 | 11110 | 0 | 111100 | 11100 | 10 | Rn | Rd
0x7E21C800 FCVTAU <V><d>, <V><n> A64 01 | 1 | 111100 | sz | 10000 | 11100 | 10 | Rn | Rd
0x2E79C800 FCVTAU <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 0 | 111100 | 11100 | 10 | Rn | Rd
0x2E21C800 FCVTAU <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 011100 | sz | 10000 | 11100 | 10 | Rn | Rd
0x1EE50000 FCVTAU <Wd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 00 | 101 | 000000 | Rn | Rd
0x9EE50000 FCVTAU <Xd>, <Hn> A64 1 | 0 | 0 | 11110 | 11 | 1 | 00 | 101 | 000000 | Rn | Rd
0x1E250000 FCVTAU <Wd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 1 | 00 | 101 | 000000 | Rn | Rd
0x9E250000 FCVTAU <Xd>, <Sn> A64 1 | 0 | 0 | 11110 | 00 | 1 | 00 | 101 | 000000 | Rn | Rd
0x1E650000 FCVTAU <Wd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 1 | 00 | 101 | 000000 | Rn | Rd
0x9E650000 FCVTAU <Xd>, <Dn> A64 1 | 0 | 0 | 11110 | 01 | 1 | 00 | 101 | 000000 | Rn | Rd

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round to Nearest with Ties to Away rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(decode_fltsize) fltval;
bits(intsize) intval;

fltval = V[n, decode_fltsize];
intval = FPToFixed(fltval, 0, TRUE, FPCR, FPRounding_TIEAWAY, intsize);
X[d, intsize] = intval;