frinta

Floating-Point Round to Integral (Nearest)

FRINTA <Hd|Sd|Dd>, <Hn|Sn|Dn>

Rounds float to nearest integral value (ties away from zero).

Details

Rounds a floating-point scalar value to the nearest integral value, with ties rounded away from zero. The rounding mode is always "round to nearest, ties away from zero" regardless of the FPCR rounding mode setting. This is an AArch64-only instruction that does not modify condition flags.

Pseudocode Operation

rounded_val ← RoundToIntegral_TiesAwayFromZero(Vn)
Vd ← rounded_val

Example

FRINTA Dd, Dn

Encoding

Binary Layout
0
0
0
11110
00
1001
100
10000
Rn
Rd
 
Format FP Data Processing
Opcode 0x1E264000
Extension Floating Point

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E798800 FRINTA <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 0 | 1111001100 | 0 | 10 | Rn | Rd
0x2E218800 FRINTA <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 0 | sz | 100001100 | 0 | 10 | Rn | Rd
0x1EE64000 FRINTA <Hd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 1001 | 100 | 10000 | Rn | Rd
0x1E264000 FRINTA <Sd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 1001 | 100 | 10000 | Rn | Rd
0x1E664000 FRINTA <Dd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 1001 | 100 | 10000 | Rn | Rd
0xC1ACE000 FRINTA { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } A64 11000001 | 1 | 0 | 101 | 10 | 0 | 111000 | Zn | 0 | Zd | 0
0xC1BCE000 FRINTA { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } A64 11000001 | 1 | 0 | 111 | 10 | 0 | 111000 | Zn | 00 | Zd | 00
0x6504A000 FRINTA <Zd>.<T>, <Pg>/M, <Zn>.<T> A64 01100101 | size | 000 | 10 | 0 | 101 | Pg | Zn | Zd

Description

Floating-point Round to Integral, to nearest with ties to Away (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);
bits(esize) operand = V[n, esize];

Elem[result, 0, esize] = FPRoundInt(operand, FPCR, FPRounding_TIEAWAY, FALSE);

V[d, 128] = result;