udiv

Unsigned Divide

UDIV <Wd>, <Wn>, <Wm>

Divides two unsigned registers.

Pseudocode Operation

if Wm == 0 then Wd ← 0 else Wd ← Wn / Wm

Example

UDIV w0, w1, w2

Encoding

Binary Layout
0
31
0
30
0
29
11010110
28:21
Rm
20:16
00001
15:11
0
10
Rn
9:5
Rd
4:0
 
Format Data Processing
Opcode 0x1AC00800
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    Dividend
  • Wm
    Divisor

Related

Other forms of udiv

  • udiv SVE Unsigned Divide
  • udiv Unsigned Divide (Thumb)
  • udiv Unsigned Divide (A32)

Across architectures

Integer Divide : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1AC00800 UDIV <Wd>, <Wn>, <Wm> A64 0 | 0 | 0 | 11010110 | Rm | 00001 | 0 | Rn | Rd
0x9AC00800 UDIV <Xd>, <Xn>, <Xm> A64 1 | 0 | 0 | 11010110 | Rm | 00001 | 0 | Rn | Rd
0x04150000 UDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 0101 | 0 | 1 | 000 | Pg | Zm | Zdn

Description

Unsigned Divide divides an unsigned integer register value by another unsigned integer register value, and writes the result to the destination register. The condition flags are not affected.

Operation

bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = X[m, datasize];
integer result;

if IsZero(operand2) then
    result = 0;
else
    result = RoundTowardsZero(Real(Int(operand1, TRUE)) / Real(Int(operand2, TRUE)));

X[d, datasize] = result<datasize-1:0>;