tst.w

Test (Wide)

TST.W <Rn>, <Operand2>

Thumb-2 32-bit Test (AND and update flags).

Details

Test (AND and update flags): computes the bitwise AND of Rn and Operand2, updating the N and Z flags based on the result without writing to a destination register. C is updated by the shifter; V is unaffected. This is a Thumb-2 (32-bit) instruction available in T32 execution state.

Pseudocode Operation

result ← Rn AND Operand2
N ← result[31]
Z ← (result == 0)
C ← CarryOut(Operand2)
V ← unchanged

Example

TST.W r1, r2

Encoding

Binary Layout
1110101
0000
1
Rn
0
imm3
1111
imm2
stype
Rm
 
Format Thumb2 Data Proc
Opcode 0xEA100F00
Extension T32 (Thumb2)

Operands

  • Rn
    First source / base general-purpose register
  • Operand2
    Flexible second operand (register or shifted register)

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x03100000 TST{<c>}{<q>} <Rn>, #<const> A32 cond | 00110 | 00 | 1 | Rn | 0 | 0 | 0 | 0 | imm12
0xF0100F00 TST{<c>}{<q>} <Rn>, #<const> T32 11110 | i | 0 | 0000 | 1 | Rn | 0 | imm3 | 1111 | imm8
0x01100060 TST{<c>}{<q>} <Rn>, <Rm>, RRX A32 cond | 00010 | 00 | 1 | Rn | 0 | 0 | 0 | 0 | 00000 | 11 | 0 | Rm
0x01100000 TST{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount>} A32 cond | 00010 | 00 | 1 | Rn | 0 | 0 | 0 | 0 | imm5 | stype | 0 | Rm
0x4200 TST{<c>}{<q>} <Rn>, <Rm> T32 010000 | 1000 | Rm | Rn
0xEA100F30 TST{<c>}{<q>} <Rn>, <Rm>, RRX T32 1110101 | 0000 | 1 | Rn | 0 | 000 | 1111 | 00 | 11 | Rm
0xEA100F00 TST{<c>}.W <Rn>, <Rm> T32 1110101 | 0000 | 1 | Rn | 0 | imm3 | 1111 | imm2 | stype | Rm
0x01100010 TST{<c>}{<q>} <Rn>, <Rm>, <type> <Rs> A32 cond | 00010 | 00 | 1 | Rn | 0 | 0 | 0 | 0 | Rs | 0 | stype | 1 | Rm

Description

Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    result = R[n] AND shifted;
    PSTATE.N = result<31>;
    PSTATE.Z = IsZeroBit(result);
    PSTATE.C = carry;
    // PSTATE.V unchanged