fnmadd

Floating-Point Fused Negated Multiply-Add (Scalar)

FNMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da>

Calculates -((Vn * Vm) + Va).

Details

Floating-point fused negated multiply-add: computes −((Vn × Vm) + Va) and stores the result in Vd as a single fused operation with a single rounding step. Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; exceptions may be generated for invalid operations, overflow, underflow, inexact results, or input denormals depending on FPCR settings. AArch64 only.

Pseudocode Operation

if HaveFPExt() then
  Vd ← FPNegMulAdd(Vn, Vm, Va)
else
  UNDEFINED

Example

FNMADD Dd, Dn, Dm, Da

Encoding

Binary Layout
0
0
0
11111
00
1
Rm
0
Ra
Rn
Rd
 
Format FP Data Processing
Opcode 0x1F200000
Extension Floating Point

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register
  • Va
    Addend

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1FE00000 FNMADD <Hd>, <Hn>, <Hm>, <Ha> A64 0 | 0 | 0 | 11111 | 11 | 1 | Rm | 0 | Ra | Rn | Rd
0x1F200000 FNMADD <Sd>, <Sn>, <Sm>, <Sa> A64 0 | 0 | 0 | 11111 | 00 | 1 | Rm | 0 | Ra | Rn | Rd
0x1F600000 FNMADD <Dd>, <Dn>, <Dm>, <Da> A64 0 | 0 | 0 | 11111 | 01 | 1 | Rm | 0 | Ra | Rn | Rd

Description

Floating-point Negated fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, subtracts the value of the third SIMD&FP source register, and writes the result to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(esize) operanda = V[a, esize];
bits(esize) operand1 = V[n, esize];
bits(esize) operand2 = V[m, esize];

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[a, 128] else Zeros(128);

operanda = FPNeg(operanda, FPCR);
operand1 = FPNeg(operand1, FPCR);
Elem[result, 0, esize] = FPMulAdd(operanda, operand1, operand2, FPCR);

V[d, 128] = result;