uhsub16

Unsigned Halving Subtract 16

UHSUB16<c> <Rd>, <Rn>, <Rm>

Unsigned halving subtract of 2 halfwords.

Details

Performs unsigned halving subtraction of two 16-bit halfwords in parallel. Each halfword of Rm is subtracted from the corresponding halfword of Rn and the result is divided by 2 (rounded down). No condition flags are affected.

Pseudocode Operation

half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]
half1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]
diff1 ← half1_rn - half1_rm; diff2 ← half2_rn - half2_rm
Rd[15:0] ← diff1 >> 1
Rd[31:16] ← diff2 >> 1

Example

UHSUB16 r0, r1, r2

Encoding

Binary Layout
cond
01100
111
Rn
Rd
1
1
1
1
0
11
1
Rm
 
Format SIMD Integer
Opcode 0x06700F70
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06700F70 UHSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> A32 cond | 01100 | 111 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm
0xFAD0F060 UHSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> T32 111110101 | 101 | Rn | 1111 | Rd | 0 | 1 | 1 | 0 | Rm

Description

Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    diff1 = UInt(R[n]<15:0>) - UInt(R[m]<15:0>);
    diff2 = UInt(R[n]<31:16>) - UInt(R[m]<31:16>);
    R[d]<15:0>  = diff1<16:1>;
    R[d]<31:16> = diff2<16:1>;