bfdot

BFloat16 Dot Product (NEON)

BFDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Computes dot product of BFloat16 elements, accumulating to Float32 (NEON).

Details

Computes the dot product of BFloat16 pairs from two NEON vectors and accumulates the Float32 result into the destination vector. Requires FEAT_BF16. No flags are affected. Operates on 128-bit NEON vectors with BFloat16 source elements.

Pseudocode Operation

for i = 0 to elements-1 do
  product ← BF16_to_F32(Vn[2*i]) × BF16_to_F32(Vm[2*i]) +
            BF16_to_F32(Vn[2*i+1]) × BF16_to_F32(Vm[2*i+1])
  Vd[i] ← Vd[i] + product
end for

Example

BFDOT v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
1
01110
01
0
Rm
1
1111
1
Rn
Rd
 
Format NEON 3-Reg
Opcode 0x2E40FC00
Extension FEAT_BF16 (AI)

Operands

  • Vd
    Dest (F32)
  • Vn
    Src1 (BF16)
  • Vm
    Src2 (BF16)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0F40F000 BFDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.2H[<index>] A64 0 | Q | 0 | 01111 | 01 | L | M | Rm | 1111 | H | 0 | Rn | Rd
0x2E40FC00 BFDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> A64 0 | Q | 1 | 01110 | 01 | 0 | Rm | 1 | 1111 | 1 | Rn | Rd
0x64608000 BFDOT <Zda>.S, <Zn>.H, <Zm>.H A64 011001000 | 1 | 1 | Zm | 10000 | 0 | Zn | Zda
0x64604000 BFDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] A64 011001000 | 1 | 1 | i2 | Zm | 0100 | 0 | 0 | Zn | Zda
0xC1501018 BFDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] A64 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 011 | off3
0xC1509018 BFDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] A64 110000010101 | Zm | 1 | Rv | 1 | i2 | Zn | 0 | 01 | 1 | off3
0xC1201010 BFDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H A64 110000010010 | Zm | 0 | Rv | 100 | Zn | 10 | off3
0xC1301010 BFDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H A64 110000010011 | Zm | 0 | Rv | 100 | Zn | 10 | off3
0xC1A01010 BFDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } A64 11 | 000001101 | Zm | 00 | Rv | 100 | Zn | 01 | 0 | off3
0xC1A11010 BFDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } A64 11 | 000001101 | Zm | 010 | Rv | 100 | Zn | 0 | 0 | 1 | 0 | off3

Description

BFloat16 floating-point dot product (vector). This instruction delimits the source vectors into pairs of BFloat16 elements. If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction: If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction: Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction: ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) operand3 = V[d, datasize];
bits(datasize) result;

for e = 0 to elements-1
    bits(16) elt1_a = Elem[operand1, 2*e+0, 16];
    bits(16) elt1_b = Elem[operand1, 2*e+1, 16];
    bits(16) elt2_a = Elem[operand2, 2*e+0, 16];
    bits(16) elt2_b = Elem[operand2, 2*e+1, 16];

    bits(32) sum = Elem[operand3, e, 32];
    sum = BFDotAdd(sum, elt1_a, elt1_b, elt2_a, elt2_b, FPCR);
    Elem[result, e, 32] = sum;

V[d, datasize] = result;