fadd

SVE Floating-Point Add

FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Adds floating-point elements under predicate.

Pseudocode Operation

for i ← 0 to VL/esize - 1
  if Pg[i] == 1 then
    Zdn[i] ← Zdn[i] + Zm[i]
  else
    Zdn[i] ← Zdn[i]  // unchanged

Example

FADD z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout
01100101
31:24
size
23:22
0
21
Zm
20:16
000
15:13
00
12:11
0
10
Zn
9:5
Zd
4:0
 
Format SVE FP Binary
Opcode 0x65000000
Extension SVE

Operands

  • Zdn
    Combined destination/source scalable vector register (SVE)
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)

Related

Other forms of fadd

  • fadd Floating-Point Add (Scalar)
  • fadd Vector Floating-Point Add
  • fadd Floating-Point Add (Half-Precision)
  • fadd Floating-point Add (Single)
  • fadd Floating-point Add (Double)

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E401400 FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 0 | 10 | Rm | 00 | 010 | 1 | Rn | Rd
0x0E20D400 FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 011100 | sz | 1 | Rm | 11010 | 1 | Rn | Rd
0x1EE02800 FADD <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 001 | 0 | 10 | Rn | Rd
0x1E202800 FADD <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 0 | 10 | Rn | Rd
0x1E602800 FADD <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 001 | 0 | 10 | Rn | Rd
0x65188000 FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> A64 01100101 | size | 011 | 00 | 0 | 100 | Pg | 0000 | i1 | Zdn
0x65008000 FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 000 | 0 | 100 | Pg | Zm | Zdn
0x65000000 FADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 00 | 0 | Zn | Zd
0xC1A01C00 FADD ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } A64 110000011 | sz | 1000000 | Rv | 111 | Zm | 00 | 0 | off3
0xC1A41C00 FADD ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } A64 110000011 | 0 | 1001000 | Rv | 111 | Zm | 00 | 0 | off3
0xC1A11C00 FADD ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } A64 110000011 | sz | 1000010 | Rv | 111 | Zm | 000 | 0 | off3
0xC1A51C00 FADD ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } A64 110000011 | 0 | 1001010 | Rv | 111 | Zm | 000 | 0 | off3

Description

Add all floating-point elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result;

for e = 0 to elements-1
    bits(esize) element1 = Elem[operand1, e, esize];
    bits(esize) element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);

Z[d, VL] = result;