smlald

Signed Multiply Accumulate Long Dual

SMLALD{X}<c> <RdLo>, <RdHi>, <Rn>, <Rm>

Dual multiply add + 64-bit accumulate.

Details

The Signed Multiply Accumulate Long Dual instruction dual multiply add + 64-bit accumulate.

Pseudocode Operation

// Dual multiply add + 64-bit accumulate

Example

SMLALD r1, r0, r1, r2

Encoding

Binary Layout
cond
01110100
Rn
RdLo
RdHi
0001
Rm
 
Format Multiply
Opcode 0x07400010
Extension A32 (DSP)

Operands

  • RdLo
    Dest Lo
  • RdHi
    Dest Hi
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register