vclt

Vector Compare Less Than

VCLT<c>.<dt> <Qd>, <Qn>, <Qm>

Compares elements (<). Alias for VCGT with swapped operands.

Pseudocode Operation

for i = 0 to (128 / element_size) - 1 do
  if Qn[i] < Qm[i] then
    Qd[i] ← all_ones
  else
    Qd[i] ← all_zeros
  end if
end for

Example

VCLT.dt q0, q1, q2

Encoding

Binary Layout

1111001

31:25

U

24

0

23

D

22

size

21:20

Vn

19:16

Vd

15:12

0011

11:8

N

7

0

6

M

5

0

4

Vm

3:0

 

Format NEON Alias

Opcode 0xF2000300

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qn
  First source 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF3B10200	VCLT{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0		A32		111100111 | D | 11 | size | 01 | Vd | 0 | F | 100 | 0 | M | 0 | Vm
0xF3B10240	VCLT{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0		A32		111100111 | D | 11 | size | 01 | Vd | 0 | F | 100 | 1 | M | 0 | Vm
0xFFB10200	VCLT{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0		T32		111111111 | D | 11 | size | 01 | Vd | 0 | F | 100 | 0 | M | 0 | Vm
0xFFB10240	VCLT{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0		T32		111111111 | D | 11 | size | 01 | Vd | 0 | F | 100 | 1 | M | 0 | Vm
0xF2000300	VCLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		A32		1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 0 | M | 0 | Vm
0xF2000340	VCLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		A32		1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 1 | M | 0 | Vm
0xF3200E00	VCLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		A32		1111001 | 1 | 0 | D | 1 | sz | Vn | Vd | 1110 | N | 0 | M | 0 | Vm
0xF3200E40	VCLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		A32		1111001 | 1 | 0 | D | 1 | sz | Vn | Vd | 1110 | N | 1 | M | 0 | Vm
0xEF000300	VCLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		T32		111 | U | 11110 | D | size | Vn | Vd | 0011 | N | 0 | M | 0 | Vm
0xEF000340	VCLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		T32		111 | U | 11110 | D | size | Vn | Vd | 0011 | N | 1 | M | 0 | Vm
0xFF200E00	VCLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		T32		111 | 1 | 11110 | D | 1 | sz | Vn | Vd | 1110 | N | 0 | M | 0 | Vm
0xFF200E40	VCLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		T32		111 | 1 | 11110 | D | 1 | sz | Vn | Vd | 1110 | N | 1 | M | 0 | Vm

Description

Vector Compare Less Than takes each element in a vector, and compares it with the corresponding element of a second vector. If the first is less than the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.