stl

Store Release (A32)

STL<c> <Rt>, [<Rn>]

Stores a word with Release semantics.

Details

Stores a 32-bit word to memory with Release semantics, ensuring all prior memory operations are visible to other observers before the store completes. No condition flags are affected. This is an A32-only instruction that provides atomic release semantics for synchronization.

Pseudocode Operation

address ← Rn
MemoryOrder ← Release
[address] ← Rt[31:0]
DRAIN_RELEASE_BARRIER()

Example

STL r3, [r1]

Encoding

Binary Layout
cond
00011
00
0
Rn
1111
1
1
0
0
1001
Rt
 
Format Load/Store
Opcode 0x0180FC90
Extension A32 (Atomic)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0180FC90 STL{<c>}{<q>} <Rt>, [<Rn>] A32 cond | 00011 | 00 | 0 | Rn | 1111 | 1 | 1 | 0 | 0 | 1001 | Rt
0xE8C00FAF STL{<c>}{<q>} <Rt>, [<Rn>] T32 11101000110 | 0 | Rn | Rt | 1111 | 1 | 0 | 10 | 1111

Description

Store-Release Word stores a word from a register to memory. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    MemO[address, 4] = R[t];