tsb

Trace Synchronization Barrier (A32)

TSB CSYNC

Ensures trace generation is complete (v8.2).

Pseudocode Operation

// Synchronize trace generation (CSYNC variant)
TraceBarrier(CSYNC)
// Trace context switches complete before proceeding

Encoding

Binary Layout

cond

31:28

00110

27:23

0

22

10

21:20

0000

19:16

1

15

1

14

1

13

1

12

000000010010

11:0

 

Format System Hint

Opcode 0x0320F012

Extension A32 (Trace)

Operands

Related

Other forms of tsb

• tsb Trace Synchronization Barrier

More in A32 (Trace)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0320F012	TSB{<c>}{<q>} CSYNC		A32		cond | 00110 | 0 | 10 | 0000 | 1 | 1 | 1 | 1 | 000000010010
0xF3AF8012	TSB{<c>}{<q>} CSYNC		T32		111100111010 | 1 | 1 | 1 | 1 | 10 | 0 | 0 | 0 | 000 | 0001 | 0010

Description

Trace Synchronization Barrier. This instruction is a barrier that synchronizes the trace operations of instructions. If FEAT_TRF is not implemented, this instruction executes as a NOP.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    TraceSynchronizationBarrier();