tsb

Trace Synchronization Barrier (A32)

TSB CSYNC

Ensures trace generation is complete (v8.2).

Details

Trace Synchronization Barrier with CSYNC operand (v8.2) ensures that trace generation is synchronized and complete before subsequent instructions execute, used to maintain consistency in trace output. This instruction is primarily used in debug and tracing scenarios and does not modify general-purpose registers or condition flags. Available in A32 instruction set.

Pseudocode Operation

// Synchronize trace generation (CSYNC variant)
TraceBarrier(CSYNC)
// Trace context switches complete before proceeding

Example

TSB CSYNC

Encoding

Binary Layout
cond
00110
0
10
0000
1
1
1
1
000000010010
 
Format System Hint
Opcode 0x0320F012
Extension A32 (Trace)

Operands

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0320F012 TSB{<c>}{<q>} CSYNC A32 cond | 00110 | 0 | 10 | 0000 | 1 | 1 | 1 | 1 | 000000010010
0xF3AF8012 TSB{<c>}{<q>} CSYNC T32 111100111010 | 1 | 1 | 1 | 1 | 10 | 0 | 0 | 0 | 000 | 0001 | 0010

Description

Trace Synchronization Barrier. This instruction is a barrier that synchronizes the trace operations of instructions. If FEAT_TRF is not implemented, this instruction executes as a NOP.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    TraceSynchronizationBarrier();