cmtst

Vector Compare Test

CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Tests if any bits match ((Vn & Vm) != 0).

Details

The Vector Compare Test instruction tests if any bits match ((Vn & Vm) != 0).

Pseudocode Operation

// Tests if any bits match ((Vn & Vm) != 0)

Example

CMTST v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
001110
size
10001
Rm
1000
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0E208C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register