vsubhn

Vector Subtract High Narrow

VSUBHN<c>.<dt> <Dd>, <Qn>, <Qm>

Subtracts wide elements and returns high narrow half.

Details

Subtracts wide elements of the second quad-width register from the first, and returns the high half of the result as narrow elements in a double-width destination. The operand size is determined by the data type specifier (sz field controls .I16, .I32, or .I64 variants). No condition flags are affected; no rounding is applied.

Pseudocode Operation

for i = 0 to (128 / (esize * 2) - 1)
  diff ← Qn[i] - Qm[i]
  Dd[i] ← (diff >> esize)[esize - 1:0]

Example

VSUBHN.dt d0, q1, q2

Encoding

Binary Layout
1111001
0
1
D
size
Vn
Vd
0110
N
0
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2800600
Extension NEON (SIMD)

Operands

  • Dd
    Dest Narrow
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800600 VSUBHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm> A32 1111001 | 0 | 1 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm
0xEF800600 VSUBHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm> T32 111 | 0 | 11111 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm

Description

Vector Subtract and Narrow, returning High Half subtracts the elements of one quadword vector from the corresponding elements of another quadword vector, takes the most significant half of each result, and places the final results in a doubleword vector. The results are truncated. For rounded results, see VRSUBHN. There is no distinction between signed and unsigned integers. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        result = Elem[Qin[n>>1],e,2*esize] - Elem[Qin[m>>1],e,2*esize];
        Elem[D[d],e,esize] = result<2*esize-1:esize>;