ld4

Load Multiple 4-Element Structures

LD4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]

Loads four-element structures (e.g., RGBA) into four registers.

Details

Loads four consecutive 4-element SIMD structures from memory, de-interleaving them into four registers (Vt1, Vt2, Vt3, Vt4). The element type T and Q field determine the 64-bit (Q=0) or 128-bit (Q=1) load size per register; the base address in Xn is post-incremented by the total bytes loaded. This AArch64 NEON instruction does not modify condition flags.

Pseudocode Operation

elements_per_struct ← 4; element_size ← GetElementSize(T); struct_bytes ← 4 * elements_per_struct * element_size; mem_addr ← Xn; (Vt1, Vt2, Vt3, Vt4) ← DeinterleaveLoad(mem_addr, struct_bytes, Q); Xn ← Xn + struct_bytes;

Example

LD4 [x1]

Encoding

Binary Layout
0
Q
0011000
1
000000
0000
size
Rn
Rt
 
Format SIMD Load/Store
Opcode 0x0C400000
Extension NEON (SIMD)

Operands

  • Vt1
    R
  • Vt2
    G
  • Vt3
    B
  • Vt4
    A

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0C400000 LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] A64 0 | Q | 0011000 | 1 | 000000 | 0000 | size | Rn | Rt
0x0CDF0000 LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm> A64 0 | Q | 0011001 | 1 | 0 | 11111 | 0000 | size | Rn | Rt
0x0CC00000 LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm> A64 0 | Q | 0011001 | 1 | 0 | Rm | 0000 | size | Rn | Rt
0x0D602000 LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>] A64 0 | Q | 0011010 | 1 | 1 | 0000 | 0 | 001 | S | size | Rn | Rt
0x0D606000 LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>] A64 0 | Q | 0011010 | 1 | 1 | 0000 | 0 | 011 | S | size | Rn | Rt
0x0D60A000 LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>] A64 0 | Q | 0011010 | 1 | 1 | 0000 | 0 | 101 | S | 00 | Rn | Rt
0x0D60A400 LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>] A64 0 | Q | 0011010 | 1 | 1 | 0000 | 0 | 101 | 0 | 01 | Rn | Rt
0x0DFF2000 LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4 A64 0 | Q | 0011011 | 1 | 1 | 11111 | 001 | S | size | Rn | Rt
0x0DE02000 LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm> A64 0 | Q | 0011011 | 1 | 1 | Rm | 001 | S | size | Rn | Rt
0x0DFF6000 LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8 A64 0 | Q | 0011011 | 1 | 1 | 11111 | 011 | S | size | Rn | Rt
0x0DE06000 LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm> A64 0 | Q | 0011011 | 1 | 1 | Rm | 011 | S | size | Rn | Rt
0x0DFFA000 LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16 A64 0 | Q | 0011011 | 1 | 1 | 11111 | 101 | S | 00 | Rn | Rt
0x0DE0A000 LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm> A64 0 | Q | 0011011 | 1 | 1 | Rm | 101 | S | 00 | Rn | Rt
0x0DFFA400 LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32 A64 0 | Q | 0011011 | 1 | 1 | 11111 | 101 | 0 | 01 | Rn | Rt

Description

Load multiple 4-element structures to four registers. This instruction loads multiple 4-element structures from memory and writes the result to the four SIMD&FP registers, with de-interleaving. For an example of de-interleaving, see LD3 (multiple structures). Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();

bits(64) address;
bits(64) eaddr;
bits(64) offs;
bits(datasize) rval;
integer tt;
constant integer ebytes = esize DIV 8;

AccessDescriptor accdesc = CreateAccDescASIMD(memop, nontemporal, tagchecked);
if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

offs = Zeros(64);
for r = 0 to rpt-1
    for e = 0 to elements-1
        tt = (t + r) MOD 32;
        for s = 0 to selem-1
            rval = V[tt, datasize];
            eaddr = GenerateAddress(address, offs, accdesc);
            if memop == MemOp_LOAD then
                Elem[rval, e, esize] = Mem[eaddr, ebytes, accdesc];
                V[tt, datasize] = rval;
            else // memop == MemOp_STORE
                Mem[eaddr, ebytes, accdesc] = Elem[rval, e, esize];
            offs = offs + ebytes;
            tt = (tt + 1) MOD 32;

if wback then
    if m != 31 then
        offs = X[m, 64];
    address = GenerateAddress(address, offs, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;