ADD

9 forms of this instruction - jump to one below, or scroll through all of them.

Add (Extended Register) #

Base

ADD <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}}

Adds a register value and a sign/zero-extended register value.

Operands

• Wd
  Destination 32-bit integer register
• Wn
  First source / base 32-bit integer register
• Wm
  Second source / offset 32-bit integer register
• extend
  Extension type

Encoding

Format Data Processing (Register)

Opcode 0x0B200000

Example

ADD Wd, Wn, w2

Pseudocode

Wd ← Wn + ExtendValue(Wm, extend, amount)

Add (Extended Register 64-bit) #

Base

ADD <Xd|SP>, <Xn|SP>, <R><m> {, <extend> {#<amount>}}

Adds a 64-bit register and an extended register value.

Operands

• Xd
  Destination 64-bit integer register
• Xn
  First source / base 64-bit integer register
• Rm
  Second source / offset general-purpose register

Encoding

Format Data Processing (Register)

Opcode 0x8B200000

Example

ADD x0, x1, Rm

Pseudocode

Xd ← Xn + ExtendValue(Rm, extend, amount)

Add (Immediate) #

Base

ADD <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>}

Adds a register value and an immediate value.

Operands

• Wd
  Destination 32-bit integer register
• Wn
  First source / base 32-bit integer register
• imm
  Immediate (12-bit)

Encoding

Format Data Processing (Immediate)

Opcode 0x11000000

Example

ADD Wd, Wn, #16

Pseudocode

Wd ← Wn + (imm << (sh * 12))

Add (Immediate 64-bit) #

Base

ADD <Xd|SP>, <Xn|SP>, #<imm> {, lsl #<shift>}

Adds a 64-bit register value and an immediate value.

Operands

• Xd
  Destination 64-bit integer register
• Xn
  First source / base 64-bit integer register
• imm
  Signed immediate value

Encoding

Format Data Processing (Immediate)

Opcode 0x91000000

Example

ADD x0, x1, #16

Pseudocode

Xd ← Xn + (imm << (sh * 12))

Add (Shifted Register) #

Base

ADD <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Adds a register value and a shifted register value.

Operands

• Wd
  Destination 32-bit integer register
• Wn
  First source / base 32-bit integer register
• Wm
  Second source / offset 32-bit integer register

Encoding

Format Data Processing (Register)

Opcode 0x0B000000

Example

ADD w0, w1, w2

Pseudocode

Wd ← Wn + ShiftReg(Wm, shift_type, shift_amount)

Add (Shifted Register 64-bit) #

Base

ADD <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

Adds a 64-bit register value and a shifted register value.

Operands

• Xd
  Destination 64-bit integer register
• Xn
  First source / base 64-bit integer register
• Xm
  Second source / offset 64-bit integer register

Encoding

Format Data Processing (Register)

Opcode 0x8B000000

Example

ADD x0, x1, x2

Pseudocode

Xd ← Xn + ShiftReg(Xm, shift_type, shift_amount)

Vector Add (Integer) #

NEON (SIMD)

ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Adds corresponding elements in two vectors.

Operands

• Vd
  Destination SIMD/FP vector register
• Vn
  First source SIMD/FP vector register
• Vm
  Second source SIMD/FP vector register

Encoding

Format SIMD Three Register

Opcode 0x0E208400

Example

ADD v0.4s.T, v1.4s.T, v2.4s.T

Pseudocode

for i = 0 to elements_in_vector - 1
  Vd[i] ← Vn[i] + Vm[i]

SVE Integer Add (Predicated) #

SVE

ADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Adds two vectors under predicate control.

Operands

• Zdn
  Dest/Src1
• Pg
  Merge Mask
• Zm
  Second source scalable vector register (SVE)

Encoding

Format SVE Integer Binary

Opcode 0x04000000

Example

ADD z0.s.T, p0/m/M, z0.s.T, z2.s.T

Pseudocode

for i in 0 to VL/element_width - 1:
  if Pg[i] == 1:
    Zdn[i] ← Zdn[i] + Zm[i]
  // else: Zdn[i] remains unchanged

Add (A32) #

A32 (Base)

ADD{S}<c> <Rd>, <Rn>, <Rm> {, <shift>}

Adds two 32-bit values.

Operands

• Rd
  Destination general-purpose register
• Rn
  First source / base general-purpose register
• Rm
  Second source / offset general-purpose register

Encoding

Format Data Proc

Opcode 0x00800000

Example

ADD r0, r1, r2

Pseudocode

result ← Rn + (Rm << shift_amount)
Rd ← result[31:0]
if S then
  N ← result[31]
  Z ← (result == 0)
  C ← CarryOut(Rn, Rm << shift_amount)
  V ← OverflowFrom(Rn, Rm << shift_amount)

Related

Across architectures

Integer Addition : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base