fneg

Floating-Point Negate (Scalar)

FNEG <Hd|Sd|Dd>, <Hn|Sn|Dn>

Negates the value (flips sign bit).

Details

Floating-point negate: flips the sign bit of Vn and stores the result in Vd, converting positive to negative and vice versa (including sign of zero). Supports half-precision (H), single-precision (S), and double-precision (D) floating-point formats. No condition flags are affected; no floating-point exceptions are generated. AArch64 only.

Pseudocode Operation

if HaveFPExt() then
  Vd ← FPNeg(Vn)
else
  UNDEFINED

Example

FNEG Dd, Dn

Encoding

Binary Layout

11110

10000

Format FP Data Processing

Opcode 0x1EE14000

Extension Floating Point

Operands

Vd
Destination SIMD/FP vector register
Vn
First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x2EF8F800	FNEG <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 1 \| 01110 \| 1 \| 111100 \| 01111 \| 10 \| Rn \| Rd
0x2EA0F800	FNEG <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 1 \| 011101 \| sz \| 10000 \| 01111 \| 10 \| Rn \| Rd
0x1EE14000	FNEG <Hd>, <Hn>	A64	0 \| 0 \| 0 \| 11110 \| 11 \| 10000 \| 10 \| 10000 \| Rn \| Rd
0x1E214000	FNEG <Sd>, <Sn>	A64	0 \| 0 \| 0 \| 11110 \| 00 \| 10000 \| 10 \| 10000 \| Rn \| Rd
0x1E614000	FNEG <Dd>, <Dn>	A64	0 \| 0 \| 0 \| 11110 \| 01 \| 10000 \| 10 \| 10000 \| Rn \| Rd
0x041DA000	FNEG <Zd>.<T>, <Pg>/M, <Zn>.<T>	A64	00000100 \| size \| 011 \| 10 \| 1 \| 101 \| Pg \| Zn \| Zd

Description

Floating-point Negate (scalar). This instruction negates the value in the SIMD&FP source register and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else 0<127:0>;

bits(esize) operand = V[n, esize];

Elem[result, 0, esize] = FPNeg(operand, FPCR);
V[d, 128] = result;