pssbb
Physical Speculative Store Bypass Barrier (A32)
PSSBB
Prevents speculation on physical resources (v8.0).
Details
Physical Speculative Store Bypass Barrier (v8.0) prevents speculative load bypassing on physical memory operations, operating at a more restrictive level than SSBB by affecting physical resource speculation. This barrier is typically used in security contexts to prevent cross-VM or cross-process speculation. Available in A32 instruction set; does not modify condition flags.
Pseudocode Operation
// Prevent speculative load bypass on physical resources
PhysicalStoreBypassBarrier()
// All prior physical stores complete before subsequent loads can execute on physical resourcesExample
PSSBB
Encoding
Binary Layout
111101010111
1
1
1
1
1
1
1
1
0
0
0
0
0100
0100
Operands
Reference (Arm AArch32 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xF57FF044 | PSSBB{<q>} | A32 | 111101010111 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0100 | 0100 | ||
| 0xF3BF8F44 | PSSBB{<q>} | T32 | 111100111011 | 1 | 1 | 1 | 1 | 10 | 0 | 0 | 1 | 1 | 1 | 1 | 0100 | 0100 |
Description
Physical Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same physical address.
The semantics of the Physical Speculative Store Bypass Barrier are:
Operation
if ConditionPassed() then
EncodingSpecificOperations();
SpeculativeStoreBypassBarrierToPA();