pssbb

Physical Speculative Store Bypass Barrier (A32)

PSSBB

Prevents speculation on physical resources (v8.0).

Pseudocode Operation

// Prevent speculative load bypass on physical resources
PhysicalStoreBypassBarrier()
// All prior physical stores complete before subsequent loads can execute on physical resources

Encoding

Binary Layout

111101010111

31:20

1

19

1

18

1

17

1

16

1

15

1

14

1

13

1

12

0

11

0

10

0

9

0

8

0100

7:4

0100

3:0

 

Format System Hint

Opcode 0xF57FF044

Extension A32 (v8.0)

Operands

Related

Other forms of pssbb

• pssbb Physical Speculation Barrier

More in A32 (v8.0)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF57FF044	PSSBB{<q>}		A32		111101010111 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0100 | 0100
0xF3BF8F44	PSSBB{<q>}		T32		111100111011 | 1 | 1 | 1 | 1 | 10 | 0 | 0 | 1 | 1 | 1 | 1 | 0100 | 0100

Description

Physical Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same physical address. The semantics of the Physical Speculative Store Bypass Barrier are:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    SpeculativeStoreBypassBarrierToPA();