fmin

Vector Floating-Point Minimum

FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Compares and returns the smaller value per element.

Details

Compares corresponding floating-point elements in two NEON vectors and places the smaller value in the destination vector for each element. No NEON flag bits are affected; this is a per-element minimum operation available in 32-bit and 64-bit floating-point forms (controlled by sz). Executes on AArch64 with NEON/ASIMD extension; the Q bit selects between 64-bit (Q=0) and 128-bit (Q=1) vector width.

Pseudocode Operation

for i = 0 to elements_in_vector-1:
  element_size = 32 if sz==0 else 64
  Vd[element][element_size-1:0] = min_fp(Vn[element][element_size-1:0], Vm[element][element_size-1:0])

Example

FMIN v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
0
01110
1
sz
1
Rm
11110
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0EA0F400
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EC03400 FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 1 | 10 | Rm | 00 | 110 | 1 | Rn | Rd
0x0EA0F400 FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 1 | sz | 1 | Rm | 11110 | 1 | Rn | Rd
0x1EE05800 FMIN <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 01 | 01 | 10 | Rn | Rd
0x1E205800 FMIN <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 01 | 10 | Rn | Rd
0x1E605800 FMIN <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 01 | 01 | 10 | Rn | Rd
0xC120A101 FMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101000 | 0100 | 0 | Zdn | 1
0xC120A901 FMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101010 | 0100 | 0 | Zdn | 0 | 1
0xC120B101 FMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } A64 11000001 | size | 1 | Zm | 0101100 | 010 | 0 | 0 | Zdn | 1
0xC120B901 FMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } A64 11000001 | size | 1 | Zm | 00101110 | 010 | 0 | 0 | Zdn | 0 | 1
0x651F8000 FMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> A64 01100101 | size | 011 | 11 | 1 | 100 | Pg | 0000 | i1 | Zdn
0x65078000 FMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 011 | 1 | 100 | Pg | Zm | Zdn

Description

Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];

    if minimum then
        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMax(element1, element2, FPCR);

V[d, datasize] = result;