ldp

Load Pair of Registers

LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>

Loads two words from memory.

Details

Load Pair of Registers loads two 32-bit words from consecutive memory locations into two registers, with optional post-index addressing. The instruction is AArch64-only, does not modify condition flags, and the two loaded values are zero-extended to 64 bits if using Wt1/Wt2 operands. The base register is updated after the load if post-index addressing is specified.

Pseudocode Operation

offset ← SignExtend(imm7 << 2, 64)
Wt1 ← ZeroExtend(Mem32[Xn], 32)
Wt2 ← ZeroExtend(Mem32[Xn + 4], 32)
Xn ← Xn + offset

Example

LDP w3, w4, [x1], #16

Encoding

Binary Layout
00
101
0
010
1
imm7
Rt2
Rn
Rt
 
Format Load/Store Pair
Opcode 0x29400000
Extension Base

Operands

  • Wt1
    Target 1
  • Wt2
    Target 2
  • Xn
    First source / base 64-bit integer register
  • imm
    Signed immediate value

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2CC00000 LDP <St1>, <St2>, [<Xn|SP>], #<imm> A64 00 | 101 | 1 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0x6CC00000 LDP <Dt1>, <Dt2>, [<Xn|SP>], #<imm> A64 01 | 101 | 1 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0xACC00000 LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm> A64 10 | 101 | 1 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0x2DC00000 LDP <St1>, <St2>, [<Xn|SP>, #<imm>]! A64 00 | 101 | 1 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0x6DC00000 LDP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]! A64 01 | 101 | 1 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0xADC00000 LDP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]! A64 10 | 101 | 1 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0x2D400000 LDP <St1>, <St2>, [<Xn|SP>{, #<imm>}] A64 00 | 101 | 1 | 010 | 1 | imm7 | Rt2 | Rn | Rt
0x6D400000 LDP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}] A64 01 | 101 | 1 | 010 | 1 | imm7 | Rt2 | Rn | Rt
0xAD400000 LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] A64 10 | 101 | 1 | 010 | 1 | imm7 | Rt2 | Rn | Rt
0x28C00000 LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm> A64 00 | 101 | 0 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0xA8C00000 LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> A64 10 | 101 | 0 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0x29C00000 LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]! A64 00 | 101 | 0 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0xA9C00000 LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! A64 10 | 101 | 0 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0x29400000 LDP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}] A64 00 | 101 | 0 | 010 | 1 | imm7 | Rt2 | Rn | Rt

Description

Load Pair of Registers calculates an address from a base register value and an immediate offset, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(64) address2;
bits(datasize) data1;
bits(datasize) data2;
constant integer dbytes = datasize DIV 8;
boolean privileged = PSTATE.EL != EL0;

AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, FALSE, privileged, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

if !signed && IsFeatureImplemented(FEAT_LSE2) then
    bits(2*datasize) full_data;
    accdesc.ispair = TRUE;
    full_data = Mem[address, 2*dbytes, accdesc];
    if BigEndian(accdesc.acctype) then
        data2 = full_data<(datasize-1):0>;
        data1 = full_data<(2*datasize-1):datasize>;
    else
        data1 = full_data<(datasize-1):0>;
        data2 = full_data<(2*datasize-1):datasize>;
else
    address2 = GenerateAddress(address, dbytes, accdesc);
    data1 = Mem[address, dbytes, accdesc];
    data2 = Mem[address2, dbytes, accdesc];
if rt_unknown then
    data1 = bits(datasize) UNKNOWN;
    data2 = bits(datasize) UNKNOWN;
if signed then
    X[t, 64] = SignExtend(data1, 64);
    X[t2, 64] = SignExtend(data2, 64);
else
    X[t, datasize] = data1;
    X[t2, datasize] = data2;

if wback then
    if wb_unknown then
        address = bits(64) UNKNOWN;
    elsif postindex then
        address = GenerateAddress(address, offset, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;