vdup
Vector Duplicate (Scalar)
VDUP<c>.<dt> <Qd>, <Dm[x]>
Duplicates a scalar value to all lanes of a vector.
Pseudocode Operation
lane_index ← imm4
element_size ← dt_in_bits
scalar_value ← Dm[lane_index]
for i = 0 to (128 / element_size - 1)
Qd[i] ← scalar_valueExample
VDUP.dt q0, Dm[x]
Encoding
Binary Layout
111100111
31:23
D
22
11
21:20
imm4
19:16
Vd
15:12
11
11:10
000
9:7
0
6
M
5
0
4
Vm
3:0
Operands
-
Qd
Destination 128-bit SIMD register -
Dm[x]
Scalar
Related
More in NEON (SIMD)
Reference
View in Arm A64 ISA Reference ↗
Arm AArch32 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0E800B10 | VDUP{<c>}{<q>}.<size> <Qd>, <Rt> | A32 | cond | 1110 | 1 | B | Q | 0 | Vd | Rt | 1011 | D | 0 | E | 1 | 0 | 0 | 0 | 0 | ||
| 0xEE800B10 | VDUP{<c>}{<q>}.<size> <Qd>, <Rt> | T32 | 11101110 | 1 | B | Q | 0 | Vd | Rt | 1011 | D | 0 | E | 1 | 0 | 0 | 0 | 0 | ||
| 0xF3B00C00 | VDUP{<c>}{<q>}.<size> <Dd>, <Dm[x]> | A32 | 111100111 | D | 11 | imm4 | Vd | 11 | 000 | 0 | M | 0 | Vm | ||
| 0xF3B00C40 | VDUP{<c>}{<q>}.<size> <Qd>, <Dm[x]> | A32 | 111100111 | D | 11 | imm4 | Vd | 11 | 000 | 1 | M | 0 | Vm | ||
| 0xFFB00C00 | VDUP{<c>}{<q>}.<size> <Dd>, <Dm[x]> | T32 | 111111111 | D | 11 | imm4 | Vd | 11 | 000 | 0 | M | 0 | Vm | ||
| 0xFFB00C40 | VDUP{<c>}{<q>}.<size> <Qd>, <Dm[x]> | T32 | 111111111 | D | 11 | imm4 | Vd | 11 | 000 | 1 | M | 0 | Vm |
Description
Duplicate vector element to vector duplicates a single element of a vector into every element of the destination vector. The scalar, and the destination vector elements, can be any one of 8-bit, 16-bit, or 32-bit fields. There is no distinction between data types. For more information about scalars see Advanced SIMD scalars. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
scalar = Elem[D[m],index,esize];
for r = 0 to regs-1
for e = 0 to elements-1
Elem[D[d+r],e,esize] = scalar;