uzp1

Vector Unzip 1

UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

De-interleaves lower halves (Selects odd elements).

Details

De-interleaves the lower halves of two vectors by selecting odd-indexed elements (every other element starting from index 1) from the concatenation of Vn and Vm. This is a pure permutation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

Pseudocode Operation

bits(128) concatenated = Vn[0 +: 64] concatenate Vm[0 +: 64];
bits(128) result;
for e = 0 to (esize/8)-1
  result[e*8 +: 8] ← concatenated[(e*2 + 1)*8 +: 8];
if Q == 0 then
  Vd ← result[0 +: 64];
else
  Vd ← result;

Example

UZP1 v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
001110
size
0
Rm
0
0
0110
Rn
Rd
 
Format SIMD Permute
Opcode 0x0E001800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E001800 UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 001110 | size | 0 | Rm | 0 | 0 | 0110 | Rn | Rd
0x05204800 UZP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T> A64 00000101 | size | 10 | Pm | 010 | 0 | 1 | 0 | 0 | Pn | 0 | Pd
0x05206800 UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 00000101 | size | 1 | Zm | 011 | 01 | 0 | Zn | Zd
0x05A00800 UZP1 <Zd>.Q, <Zn>.Q, <Zm>.Q A64 00000101101 | Zm | 000 | 0 | 1 | 0 | Zn | Zd

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operandl = V[n, datasize];
bits(datasize) operandh = V[m, datasize];
bits(datasize) result;

bits(datasize*2) zipped = operandh:operandl;
for e = 0 to elements-1
    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];

V[d, datasize] = result;